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DISCRETE SEMICONDUCTORS
DATA SHEET
ook, halfpage
MBD128
BF1102
Dual N-channel dual gate MOS-FET
Preliminary specification
1999 Jul 08
Philips Semiconductors
Preliminary specification
Dual N-channel dual gate MOS-FET
BF1102
FEATURES
•
PINNING - SOT363
Two low noise gain controlled amplifiers in a single
package
PIN
DESCRIPTION
1
gate 1 (1)
Specially designed for 5 V applications
•
2
gate 2 (1,2)
•
Superior cross-modulation performance during AGC
3
drain (1)
•
High forward transfer admittance
4
drain (2)
•
High forward transfer admittance to input capacitance
ratio.
5
source (1,2)
6
gate 1 (2)
APPLICATIONS
•
Gain controlled low noise amplifier for VHF and UHF
applications such as television tuners and professional
communications equipment.
handbook, halfpage
g
2
(1, 2)
6
5
4
DESCRIPTION
g
1
(1)
AMP1
d (1)
The BF1102 is a combination of two equal dual gate
MOS-FETs with shared source and gate 2 leads.
The source and substrate are interconnected. An internal
bias circuit enables DC stabilization and a very good
cross-modulation performance at 5 V supply voltage.
Integrated diodes between the gates and source protect
against excessive input voltage surges. The transistor has
a SOT363 micro-miniature plastic package.
g
1
(2)
AMP2
d (2)
1
2
3
Marking code: W1.
s (1, 2)
MBL029
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Per MOS-FET unless otherwise specified
V
DS
drain-source voltage
−
−
7
V
I
D
drain current (DC)
−
−
40
mA
P
tot
total power dissipation
T
s
≤
102
°
C; note 1
−
−
200
mW
y
fs
forward transfer admittance
I
D
=15mA
−
43
−
mS
C
ig1-s
input capacitance at gate 1
I
D
=15mA
−
2.8
−
pF
C
rss
reverse transfer capacitance
f = 1 MHz
−
30
−
fF
F
noise figure
f = 800 MHz
−
−
2.8
dB
X
mod
cross-modulation
input level for k = 1% at 40 dB AGC 100
−
−
dB
µ
V
T
j
operating junction temperature
−
−
150
°
C
Note
1. T
s
is the temperature at the soldering point of the source lead.
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
1999 Jul 08
2
Philips Semiconductors
Preliminary specification
Dual N-channel dual gate MOS-FET
BF1102
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per MOS-FET unless otherwise specified
V
DS
drain-source voltage
−
7
V
I
D
drain current (DC)
−
40
mA
I
G1
gate 1 current
−
±
10
mA
I
G2
gate 2 current
−
±
10
mA
P
tot
total power dissipation
T
s
≤
102
°
C
−
200
mW
T
stg
storage temperature
−
65
+150
°
C
T
j
operating junction temperature
−
+150
°
C
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
R
th j-s
thermal resistance from junction to soldering point
240
K/W
MGS359
250
handbook, halfpage
P
tot
(mW)
200
150
100
50
0
0
50
100
150
T
s
(
°
C)
200
Fig.2 Power derating curve.
1999 Jul 08
3
Philips Semiconductors
Preliminary specification
Dual N-channel dual gate MOS-FET
BF1102
STATIC CHARACTERISTICS
T
j
=25
°
C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
Per MOS-FET unless otherwise specified
V
(BR)DSS
drain-source breakdown voltage V
G1-S
=V
G2-S
=0; I
D
=10
µ
A
7
−
V
V
(BR)G1-SS
gate-source breakdown voltage V
GS
=V
DS
=0; I
G1-S
=10mA
6
15
V
V
(BR)G2-SS
gate-source breakdown voltage V
GS
=V
DS
=0; I
G2-S
=5mA
6
15
V
V
(F)S-G1
forward source-gate voltage
V
G2-S
=V
DS
=0; I
S-G1
=
−
10 mA
0.5
1.5
V
V
(F)S-G2
forward source-gate voltage
V
G1-S
=V
DS
=0; I
S-G2
=
−
10 mA
0.5
1.5
V
V
G1-S(th)
gate-source threshold voltage
V
DS
=5V; V
G2-S
=4V; I
D
=20
µ
A
0.3
1
V
V
G2-S(th)
gate-source threshold voltage
V
DS
=5V; V
G1-S
=4V; I
D
=20
µ
A
0.3
1.2
V
I
DSX
drain-source current
V
G2-S
=4V; V
DS
=5V; R
G
= 120 k
Ω;
note 1 12
20
mA
I
G1-S
gate cut-off current
V
G1-S
=5V; V
G2-S
=V
DS
=0
−
50
nA
I
G2-S
gate cut-off current
V
G2-S
=5V; V
G1-S
=V
DS
=0
−
20
nA
Notes
1. R
G1
connects gate 1 to V
GG
=5V.
DYNAMIC CHARACTERISTICS
Common source; T
amb
=25
°
C; V
G2-S
=4V; V
DS
=5V; I
D
= 15 mA; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Per MOS-FET unless otherwise specified
(note 1)
y
fs
forward transfer admittance T
j
=25
°
C
36
43
50
S
C
ig1-ss
input capacitance at gate 1 f = 1 MHz
2
2.8
3.6
pF
C
ig2-ss
input capacitance at gate 2 f = 1 MHz
−
−
7
pF
C
oss
output capacitance
f = 1 MHz
−
1.6
2.5
pF
C
rss
reverse transfer capacitance f = 1 MHz
−
30
50
fF
F
noise figure
f = 800 MHz; Y
S
=Y
Sopt
−
2
2.8
dB
X
mod
cross-modulation
input level for k = 1% at 0 dB AGC;
f
w
=50MHz; f
unw
=60MHz; (note2)
85
−
−
dB
µ
V
input level for k = 1% at 40 dB AGC;
f
w
=50MHz; f
unw
=60MHz; (note2)
100
−
−
dB
µ
V
Notes
1. Not used MOS-FET: V
G1-S
=0; V
DS
=0.
2. Measured in test circuit of Fig.17.
1999 Jul 08
4
Philips Semiconductors
Preliminary specification
Dual N-channel dual gate MOS-FET
BF1102
ALL GRAPHS FOR ONE MOS-FET
30
MGS360
MGS361
30
V
G2-S
= 4 V
handbook, halfpage
2.5 V
handbook, halfpage
I
D
(mA)
3.5 V
I
D
(mA)
V
G1-S
= 1.5 V
3 V
2 V
20
20
1.4 V
1.3 V
1.2 V
1.5 V
10
10
1.1 V
1 V
1 V
0
0
0
0.4
0.8
1.2
1.6
2.0
2.4
0
2
4
6
8
10
V
G1-S
(V)
V
DS
(V)
V
DS
=5V.
T
j
=25
°
C.
V
G2-S
=4V.
T
j
=25
°
C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
MGS362
MGS363
160
50
handbook, halfpage
handbook, halfpage
V
G2-S
= 4 V
V
G2-S
= 4 V
I
G1
(
|y
fs
|
(mS)
3.5 V
µ
A)
40
3.5 V 3 V
120
3 V
30
80
2.5 V
2.5 V
20
40
2 V
10
2 V
0
0
0
0.5
1
1.5
2
2.5
0
10
20
30
I
D
(mA)
V
G1-S
(V)
V
DS
=5V.
T
j
=25
°
C.
V
DS
=5V.
T
j
=25
°
C.
Fig.5 Gate 1 current as a function of gate 1
voltage; typical values.
Fig.6 Forward transfer admittance as a
function of drain current; typical values.
1999 Jul 08
5
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