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L7: Memory Basics and Timing
Acknowledgements:
Materials in this lecture are courtesy of the following sources and are used with permission.
Nathan Ickes
Rex Min
Yun Wu
J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective.
Prentice Hall/Pearson, 2003.
L7: 6.111 Spring 2006
Introductory Digital Systems Laboratory
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Memory Classification & Metrics
Read-Write Memory
Non-Volatile
Read-Write
Memory
Read-Only
Memory (ROM)
Random
Access
Non-Random
Access
EPROM
Mask-Programmed
E 2 PROM
SRAM
FIFO
FLASH
DRAM
LIFO
Key Design Metrics:
1. Memory Density (number of bits/ μ m 2 ) and Size
2. Access Time (time to read or write) and Throughput
3. Power Dissipation
L7: 6.111 Spring 2006
Introductory Digital Systems Laboratory
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Memory Array Architecture
2 L-K
Bit Line
Storage Cell
A K
A K+1
Word Line
2 L-K row
by
Mx2 K column
cell array
A L-1
M.2 K
Sense Amps/Driver
Amplify swing to
rail-to-rail amplitude
A 0
Column Decode
A K-1
Selects appropriate word
(i.e., multiplexor)
Input-Output
(M bits)
L7: 6.111 Spring 2006
Introductory Digital Systems Laboratory
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Latch and Register Based Memory
Positive Latch Negative Latch
Register Memory
Negative latch
Positive latch
D
Q
D
Q
D
Q
Q M
0
1
D
Q
D
Q
G
G
1
0
Clk
CLK
CLK
Works fine for small memory blocks (e.g., small register files)
Inefficient in area for large memories – density is the key
metric in large memory circuits
How do we minimize cell size?
L7: 6.111 Spring 2006
Introductory Digital Systems Laboratory
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Static RAM (SRAM) Cell (The 6- T Cell)
T Cell)
BL
BL
WL
WL
V DD
WL
M 2
M 4
M 5
Q
Q
M 6
Q
Q
M 1
M 3
Write: set BL and BL to 0 and V DD
or V DD and 0 and then enable WL (i.e.,
set to V DD )
Read: Charge BL and BL to V DD
and then enable WL (i.e., set to V DD ).
Sense a small change in BL or BL
BL
BL
State held by cross-coupled inverters (M1-M4)
Static Memory - retains state as long as power supply turned on
Feedback must be overdriven to write into the memory
L7: 6.111 Spring 2006
Introductory Digital Systems Laboratory
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Static RAM (SRAM) Cell (The 6
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