VGA Board LS-354JP( NVidia NB8x).pdf

(322 KB) Pobierz
A
B
C
D
E
1
1
Compal confidential
2
2
Schematics Document
LS-354JP VGA BD
NVidia NB8x Solution
3
3
2006-08-28
REV:1.0
4
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2005/08/29
2006/08/29
SCHEMATIC, VGA/B LS-354JP
Title
Issued Date
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Document Number
Rev
Custom
B
4059G1
Date:
݋ಂ六 ̬˜
14, 20
07
Sheet
1
of
13
A
B
C
D
E
 
5
4
3
2
1
+1.8VS_LDO
B+
JP1
MAX. 6.5A @ +1.8VS_LDO
ZZZ1
PCIE_GTX_C_MRX_P[0:15]
1
2
PWR_SRC_A1
+1.8VRUN_B1
PCIE_GTX_C_MRX_P[0:15]
<3>
3
4
1
1
PWR_SRC_A2
+1.8VRUN_B2
C303
C304
PCIE_GTX_C_MRX_N[0:15]
5
6
PWR_SRC_A3
+1.8VRUN_B3
PCIE_GTX_C_MRX_N[0:15]
<3>
7
8
PWR_SRC_A4
+1.8VRUN_B4
9
10
PWR_SRC_A5
+1.8VRUN_B5
2
2
PCIE_MTX_C_GRX_P[0:15]
11
12
PWR_SRC_A6
+1.8VRUN_B6
PCIE_MTX_C_GRX_P[0:15]
<3>
PCB
13
14
PWR_SRC_A7
+1.8VRUN_B7
PCIE_MTX_C_GRX_N[0:15]
15
16
SUSP#
<11>
PWR_SRC_A8
RUNPWROK
PCIE_MTX_C_GRX_N[0:15]
<3>
11/8 Modified pn to DA800008E00
17
18
+5VS
GND_A9
+5VRUN
19
20
GND_A10
GND_B10
ZZZ2
21
22
GND_A11
GND_B11
23
24
Mechanical Key
GND_A12
GND_B12
D
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N10
FM1
FM2
FM3
FM4
D
25
26
PERn15
PRSNT2#
27
28
PCIE_MTX_C_GRX_N15
1
1
1
1
PERp15
PETn15
PCIE_MTX_C_GRX_P15
FM5
FM6
29
30
GND_A21
PETp15
X76
@
31
32
1
1
PERn14
GND_B22
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P13
33
34
PERp14
PETn14
35
36
GND_A24
PETp14
37
38
PERn13
GND_B25
39
40
PERp13
PETn13
41
42
GND_A27
PETp13
43
44
PERn12
GND_B28
PCIE_MTX_C_GRX_N12
45
46
PERp12
PETn12
PCIE_MTX_C_GRX_P12
47
48
GND_30
PETp12
49
50
PERn11
GND_B31
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P11
H1
HOLEA
H2
HOLEA
H3
HOLEA
H4
HOLEA
H5
HOLEA
H6
HOLEA
51
52
PERp11
PETn11
53
54
GND_A33
PETp11
55
56
PERn10
GND_B34
PCIE_GTX_C_MRX_P10
57
58
PCIE_MTX_C_GRX_N10
PERp10
PETn10
PCIE_MTX_C_GRX_P10
59
60
GND_A36
PETp10
PCIE_GTX_C_MRX_N9
61
62
PERn9
GND_B37
PCIE_GTX_C_MRX_P9
PCIE_MTX_C_GRX_N9
63
64
PERp9
PETn9
PCIE_MTX_C_GRX_P9
65
66
GND_A39
PETp9
PCIE_GTX_C_MRX_N8
67
68
PERn8
GND_B40
PCIE_GTX_C_MRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P5
69
70
PERp8
PETn8
71
72
GND_A42
PETp8
PCIE_GTX_C_MRX_N7
73
74
PERn7
GND_B43
PCIE_GTX_C_MRX_P7
75
76
PERp7
PETn7
77
78
GND_A45
PETp7
PCIE_GTX_C_MRX_N6
79
80
PERn6
GND_B46
PCIE_GTX_C_MRX_P6
81
82
PERp6
PETn6
83
84
GND_A48
PETp6
PCIE_GTX_C_MRX_N5
85
86
PERn5
GND_B49
PCIE_GTX_C_MRX_P5
87
88
PERp5
PETn5
C
C
89
90
GND_A51
PETp5
+3VS
PCIE_GTX_C_MRX_N4
91
92
PERn4
GND_B52
PCIE_GTX_C_MRX_P4
PCIE_MTX_C_GRX_N4
NVidia suggestion
93
94
PERp4
PETn4
PCIE_MTX_C_GRX_P4
LCD/PANEL BD. Conn.
95
96
CARD_COMP <3>
CARD_LUMA <3>
CARD_CRMA <3>
GND_A54
PETp4
PCIE_GTX_C_MRX_N3
97
98
PERn3
GND_B55
PCIE_GTX_C_MRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P1
99
100
PERp3
PETn3
R1
2.2K_0402_5%
R2
101
102
GND_A57
PETp3
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2
103
104
PERn2
GND_B58
@
@
2.2K_0402_5%
105
106
PERp2
PETn2
<3>
LVDSA0-
107
108
LVDSB0- <3>
GND_A60
PETp2
CARD_DDCCLK
PCIE_GTX_C_MRX_N1
109
110
<3>
LVDSA0+
CARD_DDCCLK <3>
PERn1
GND_B61
LVDSB0+ <3>
LVDSB1- <3>
CARD_DDCDATA
PCIE_GTX_C_MRX_P1
111
112
CARD_DDCDATA <3>
PERp1
PETn1
113
114
<3>
LVDSA1-
GND_A63
PETp1
+3VS
PCIE_GTX_C_MRX_N0
115
116
<3>
LVDSA1+
LVDSB1+ <3>
PERn0
GND_B64
PCIE_GTX_C_MRX_P0
PCIE_MTX_C_GRX_N0
117
118
PERp0
PETn0
PCIE_MTX_C_GRX_P0
119
120
<3>
LVDSA2-
GND_A66
PETp0
LVDSB2- <3>
121
122
<3>
LVDSA2+
<3>
CLK_PCIE_VGA#
REFCLK-
PRSNT1#
LVDSB2+ <3>
CARD_CRMA
CARD_LUMA
CARD_COMP
CARD_VGA_R
CARD_VGA_G
CARD_VGA_B
LVDSBC-
LVDSBC+
123
124
<3>
CLK_PCIE_VGA
REFCLK+
TV_CR_PR
125
126
<3>
LVDSAC-
LVDSBC- <3>
RSVD_A69
GND_B69
127
128
<3>
LVDSAC+
<3>
PLTRST_VGA#
PERST#
TV_Y_G
LVDSBC+
<3>
R395
2.2K_0402_5%
R396
(120 MIL)
129
130
RSVD_A71
GND_B71
131
132
RSVD_A72
TV_COMP_B_PB
B+
@
@
2.2K_0402_5%
133
134
<4>
SMB_DAT
SMB_DAT
GND_B73
135
136
<4>
SMB_CLK
SMB_CLK
VGA_RED
137
138
<3>
CARD_HSYNC
THER_ALERT#
THERM#
GND_B75
139
140
<3>
VGA_HSYNC
VGA_GRN
C2
0.022U_0402_25V4K
1
141
142
<3>
CARD_VSYNC
VGA_VSYNC
GND_B77
SMB_CLK
SMB_DAT
CARD_DDCCLK
143
144
2
VGA_DDCCLK
VGA_BLU
CARD_DDCDATA
145
146
VGA_DDCDAT
GND_B79
147
148
RSVD_A80
LVDS_UCLK-
C4
0.022U_0402_25V4K
1
MAX. 655mA @ 3.3V
149
150
RSVD_A81
LVDS_UCLK+
151
152
2
GND_A82
GND_B82
B
B
153
154
RSVD_A83
LVDS_UTX3-
+3VS
+5VS
155
156
RSVD_A84
LVDS_UTX3+
157
158
<3>
AC_DET
RSVD_A85
GND_B85
SPDIF <3>
LVDSB2-
40mil
159
160
RSVD_A86
LVDS_UTX2-
LVDSB2+
161
162
RSVD_A87
LVDS_UTX2+
163
164
GND_A88
GND_B88
165
166
LVDSB1-
RSVD_A89
LVDS_UTX1-
R281
10K_0402_5%
LVDSB1+
167
168
1
1
1
1
RSVD_A90
LVDS_UTX1+
169
170
place the bypass capacitor around B+ trace.
GND_A91
GND_B91
LVDSB0-
171
172
RSVD_A92
LVDS_UTX0-
LVDSB0+
173
174
<3>
CARD_VGA_R
RSVD_A93
LVDS_UTX0+
2
2
2
2
175
176
GND_A94
GND_B94
LVDSAC-
177
178
<3>
CARD_VGA_G
RSVD_A95
LVDS_LCLK-
LVDSAC+
179
180
RSVD_A96
LVDS_LCLK+
181
182
<3>
CARD_VGA_B
RSVD_A97
GND_B97
183
184
RSVD_A98
LVDS_LTX3-
185
186
RSVD_A99
LVDS_LTX3+
187
188
GND_A100
GND_B100
LVDSA2-
189
190
RSVD_A101
LVDS_LTX2-
191
192
LVDSA2+
RSVD_A102
LVDS_LTX2+
ENVDD <3>
193
194
GND_A103
GND_B103
195
196
LVDSA1-
RSVD_A104
LVDS_LTX1-
LVDSA1+
197
198
RSVD_A105
LVDS_LTX1+
199
200
GND_A106
GND_B106
LVDSA0-
201
202
RSVD_A107
LVDS_LTX0-
LVDSA0+
203
204
RSVD_A108
LVDS_LTX0+
205
206
<3>
DVI_DET
DVI_HPD
GND_B109
207
208
<3>
DVI_CLK#
EDID_DAT_LCD <3>
EDID_CLK_LCD <3>
DVI_CLK-
I2C_DAT
209
210
<3>
DVI_CLK
DVI_CLK+
I2C_CLK
211
212
GND_A112
LVDS_DIGON
213
214
<3>
DVI_TXN2
DVI_TX2-
LVDS_PWM
BL_BRIGHT
<3>
215
216
<3>
DVI_TXP2
G7X_ENBKL <3>
DVI_TX2+
LVDS_BLON
A
+2.5VS
MAX. 130mA @ 2.5V
A
217
218
GND_A115
DVI_SDAT
219
220
<3>
DVI_TXN1
DVI_TX1-
DVI_SCLK
221
222
+3VS
<3>
DVI_TXP1
DVI_TX1+
+2.5VRUN
223
224
GND_A118
GND_B118
225
226
R288
10K_0402_5%
<3>
DVI_TXN0
DVI_TX0-
+3.3VRUN_B119
R100
10K_0402_5%
R101
10K_0402_5%
227
228
<3>
DVI_TXP0
DVI_TX0+
+3.3VRUN_B120
229
230
GND_A121
+3.3VRUN_B121
Compal Electronics, Inc.
@
ACES_88990-2D28_230_GF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
Title
DVI_DDCDAT <3>
DVI_DDCCLK <3>
SCHEMATIC, VGA/B LS-354JP
DVI/HDMI IFXXX
havn't tested
PCB Footprint = ACES_88990-2D28_230P_GF
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
Size
Document Number
Rev
4059G1
Custom
B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
Date:
݋ಂ六 ̬˜
14, 2007
Sheet
2
of
13
5
4
3
2
1
 
5
4
3
2
1
U1
U1
U1
U1
DVI_DET <2>
U1A
R35
10K_0402_5%
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
Part 1 of 6
AK13
K3
1
2
PEX_RX0
GPIO0
A K14
H1
PEX_RX0_N
GPIO1
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_P1
NB8PGS_BGA820
NB8PGS@
NB8MGS_BGA820
NB8MGS@
G73M_BGA820
G73@
G72MV_BGA820
G72MV@
AM14
K5
<2>
PCIE_MTX_C_GRX_N[0..15]
PEX_RX1
GPIO2
BL_BRIGHT
<2>
PCIE_MTX_C_GRX_N1
ENVDD
A M15
G5
ENVDD <2>
PEX_RX1_N
GPIO3
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
AL15
E2
<2>
PCIE_MTX_C_GRX_P[0..15]
PEX_RX2
GPIO4
G7X_ENBKL <2>
SUSP#_GFX_CNTRL
AL16
J5
POWER_SEL
<11>
PEX_RX2_N
GPIO5
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
PCIE_MTX_C_GRX_P3
AK16
G6
<2>
PCIE_GTX_C_MRX_N[0..15]
PEX_RX3
GPIO6
GPIO8
U1D
AK17
K6
PEX_RX3_N
GPIO7
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
A L17
E1
THER_ALERT#
LVDSAC+
AK9
B32
<2>
LVDSAC+
<2>
PCIE_GTX_C_MRX_P[0..15]
PEX_RX4
GPIO8
THER_ALERT#
<2>
IFPA_TXC
NC_0
D
PCIE_MTX_C_GRX_N4
LVDSAC-
Part 4 of 6
D
AL18
D2
AJ9
C20
<2>
LVDSAC-
PEX_RX4_N
GPIO9
IFPA_TXC_N
NC_1
A M18
H5
R3
1
2
2K_0402_5%
LVDSA0+
AH6
D1
+3VS
<2>
LVDSA0+
PEX_RX5
GPIO10
IFPA_TXD0
NC_2
LVDSA0-
AM19
F4
AJ6
J6
<2>
LVDSA0-
SPDIF <2>
PEX_RX5_N
GPIO11
IFPA_TXD0_N
NC_3
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
A K19
E3
LVDSA1+
LVDSA1-
AH8
U3
<2>
LVDSA1+
PEX_RX6
GPIO12
AC_DET
<2>
IFPA_TXD1
NC_4
AK20
AH7
U4
<2>
LVDSA1-
PEX_RX6_N
IFPA_TXD1_N
NC_5
PEX_PLL_TERM
LVDSA2+
A L20
P2
AJ8
U5
PEX_RX7
MIOAD0
PEX_PLL_TERM <6>
SUB_VENDOR <6>
<2>
LVDSA2+
IFPA_TXD2
NC_6
SUB_VENDOR
LVDSA2-
AL21
N2
AK8
U6
<2>
LVDSA2-
PEX_RX7_N
MIOAD1
IFPA_TXD2_N
NC_7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
A M21
N1
AJ5
V1
PEX_RX8
MIOAD2
IFPA_TXD3
NC_8
AM22
N3
AH5
V3
PEX_RX8_N
MIOAD3
IFPA_TXD3_N
NC_9
LVDSBC+
AK22
M1
AK4
V4
<2>
LVDSBC+
PEX_RX9
MIOAD4
IFPB_TXC
NC_10
LVDSBC-
AK23
M3
AL4
V5
<2>
LVDSBC-
PEX_RX9_N
MIOAD5
IFPB_TXC_N
NC_11
PCIE_MTX_C_GRX_P10
PEX_CFG0
LVDSB0+
LVDSB1+
AL23
P5
AM6
V6
PEX_CFG0 <6>
<2>
LVDSB0+
PEX_RX10
MIOAD6
IFPB_TXD4
NC_12
LVDSB0-
LVDSB1-
AL24
N6
AM5
W1
<2>
LVDSB0-
PEX_RX10_N
MIOAD7
IFPB_TXD4_N
NC_13
PCIE_MTX_C_GRX_P11
PEX_CFG1
PEX_CFG2
AM24
N5
AM7
W3
PEX_CFG1 <6>
<2>
LVDSB1+
PEX_RX11
MIOAD8
IFPB_TXD5
NC_14
PCIE_MTX_C_GRX_N11
A M25
M4
AL7
W4
<2>
LVDSB1-
PEX_RX11_N
MIOAD9
PEX_CFG2 <6>
IFPB_TXD5_N
NC_15
PCIE_MTX_C_GRX_P12
LVDSB2+
AK25
L4
AK6
W5
<2>
LVDSB2+
PEX_RX12
MIOAD10
IFPB_TXD6
NC_16
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
A K26
L5
LVDSB2-
AK5
Y5
<2>
LVDSB2-
PEX_RX12_N
MIOAD11
IFPB_TXD6_N
NC_17
AL26
AK7
Y6
PEX_RX13
IFPB_TXD7
NC_18
A L27
R3
1
2
AL8
Y30
PEX_RX13_N
MIOA_HSYNC
IFPB_TXD7_N
NC_19
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
R6
2K_0402_5%
AM27
R1
AC26
PEX_RX14
MIOA_VSYNC
NC_20
R4
@
1K_0402_5%
A M28
P1
1
2
AL5
AG12
PEX_RX14_N
MIOA_DE
IFPAB_RSET
NC_21
AL28
P3
AH13
PEX_RX15
MIOA_CTL3
NC_22
AL29
AM2
AM8
<2>
DVI_CLK
PEX_RX15_N
IFPC_TXC
NC_23
R7
10K_0402_5%
M5
2
1
AM3
AM9
MIOA_CLKIN
<2>
DVI_CLK#
IFPC_TXC_N
NC_24
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
C9
0.1U_0402_10V7K
PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_N1
1
2
AJ15
R4
AE2
F1
<2>
DVI_TXP0
PEX_TX0
MIOA_CLKOUT
IFPC_TXD0
NC_25
C10
0.1U_0402_10V7K
1
2
AK15
P4
AE1
PEX_TX0_N
MIOA_CLKOUT_N
<2>
DVI_TXN0
IFPC_TXD0_N
PCIE_GTX_C_MRX_P1
C11
0.1U_0402_10V7K
PCIE_GTX_MRX_P1
1
2
AH16
AF1
F3
<2>
DVI_TXP1
PEX_TX1
IFPC_TXD1
BUFRST_N
PCIE_GTX_C_MRX_N1
C12
1
2
0.1U_0402_10V7K
A G16
L2
AF2
AE26
PEX_TX1_N
MIOA_VREF
<2>
DVI_TXN1
IFPC_TXD1_N
MEMSTRAPSEL0
PCIE_GTX_C_MRX_P2
C13
0.1U_0402_10V7K
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3
FAE recommand 6/29
1
2
AG17
AG1
AD26
<2>
DVI_TXP2
PEX_TX2
IFPC_TXD2
MEMSTRAPSEL1
PCIE_GTX_C_MRX_N2
C14
1
2
0.1U_0402_10V7K
PCIE_GTX_MRX_N2
A H17
AC3
RAM_CFG0
AH1
AH31
PEX_TX2_N
MIOBD0
RAM_CFG0 <6>
<2>
DVI_TXN2
IFPC_TXD2_N
MEMSTRAPSEL2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
C15
0.1U_0402_10V7K
RAM_CFG1
1
2
AG18
AC1
AG3
AH32
RAM_CFG1 <6>
PEX_TX3
MIOBD1
IFPD_TXC
MEMSTRAPSEL3
C16
1
2
0.1U_0402_10V7K
A H18
AC2
CRYSTAL_0
AH2
T3
PEX_TX3_N
MIOBD2
IFPD_TXC_N
STEREO
C
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
C17
0.1U_0402_10V7K
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5
PCI_DEVID2
C
1
2
AK18
AB2
AK1
PCI_DEVID2 <6>
PCI_DEVID0 <6>
PCI_DEVID1 <6>
PEX_TX4
MIOBD3
IFPD_TXD4
C18
0.1U_0402_10V7K
PCIE_GTX_MRX_N4
PCI_DEVID0
PCI_DEVID1
1
2
A J18
AB1
AJ1
M6
PEX_TX4_N
MIOBD4
IFPD_TXD4_N
SWAPRDY_A
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
C19
0.1U_0402_10V7K
1
2
AJ19
AA1
AL2
J1
PEX_TX5
MIOBD5
IFPD_TXD5
THERMDN
C20
0.1U_0402_10V7K
CRYSTAL_1
1
2
A H19
AB3
AL1
K1
PEX_TX5_N
MIOBD6
IFPD_TXD5_N
THERMDP
PCIE_GTX_C_MRX_P6
C21
0.1U_0402_10V7K
PCIE_GTX_MRX_P6
1
2
AG20
AA3
AJ2
PEX_TX6
MIOBD7
PCI_IOBAR <6>
IFPD_TXD6
PCIE_GTX_C_MRX_N6
C22
0.1U_0402_10V7K
PCIE_GTX_MRX_N6
RAM_CFG2
1
2
AH20
AC5
AJ3
AA7
RAM_CFG2 <6>
RAM_CFG3 <6>
PCI_DEVID3 <6>
SCLK <6>
SIN <6>
SOUT <6>
SCS# <6>
PEX_TX6_N
MIOBD8
IFPD_TXD6_N
ROM_SCLK
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
C23
0.1U_0402_10V7K
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8
RAM_CFG3
1
2
AG21
AB5
W2
PEX_TX7
MIOBD9
ROM_SI
C24
0.1U_0402_10V7K
PCIE_GTX_MRX_N7
R8
@
1K_0402_5%
SERIAL
1
2
AH21
AB4
1
2
AH3
AA6
PEX_TX7_N
MIOBD10
IFPCD_RSET
ROM_SO
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCI_DEVID3
C25
1
2
0.1U_0402_10V7K
AK21
AA5
AA4
PEX_TX8
MIOBD11
ROMCS_N
C26
0.1U_0402_10V7K
1
2
AJ21
PEX_TX8_N
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
C27
1
2
0.1U_0402_10V7K
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_N10
A J22
AF3
PEX_TX9
MIOB_HSYNC
PEX_CFG3
<6>
C28
0.1U_0402_10V7K
G72M_BGA820
G72M@
1
2
AH22
AE3
PEX_TX9_N
MIOB_VSYNC
PCIE_GTX_C_MRX_P10
C29
1
2
0.1U_0402_10V7K
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P12
A G23
AD1
PEX_TX10
MIOB_DE
BAR2_SIZE <6>
PCIE_GTX_C_MRX_N10
C30
0.1U_0402_10V7K
1
2
AH23
AD3
PCI_DEVID4 <6>
PEX_TX10_N
MIOB_CTL3
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
C31
0.1U_0402_10V7K
1
2
A K24
PEX_TX11
C32
0.1U_0402_10V7K
R9
10K_0402_5%
1
2
AJ24
AE4
2
1
PEX_TX11_N
MIOB_CLKIN
PCIE_GTX_C_MRX_P12
C33
0.1U_0402_10V7K
VGA termination, close chip
1
2
A J25
AD4
PEX_TX12
MIOB_CLKOUT
PCIE_GTX_C_MRX_N12
C34
0.1U_0402_10V7K
PCIE_GTX_MRX_N12
CARD_LUMA
CARD_COMP
R10
150_0402_1%
1
2
AH25
AD5
1
2
PEX_TX12_N
MIOB_CLKOUT_N
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
C35
0.1U_0402_10V7K
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N15
CARD_CRMA
R11
150_0402_1%
1
2
AH26
1
2
PEX_TX13
C36
0.1U_0402_10V7K
R12
150_0402_1%
1
2
AG26
Y2
1
2
PEX_TX13_N
MIOB_VREF
C37
0.1U_0402_10V7K
1
2
AK27
PEX_TX14
C38
0.1U_0402_10V7K
CARD_HSYNC
CARD_VSYNC
CARD_VGA_R
CARD_VGA_G
CARD_VGA_B
R13
150_0402_1%
1
2
AJ27
AF10
1
2
CARD_HSYNC <2>
CARD_VSYNC <2>
CARD_VGA_R <2>
CARD_VGA_G <2>
PEX_TX14_N
DACA_HSYNC
PCIE_GTX_C_MRX_P15
C39
0.1U_0402_10V7K
R14
150_0402_1%
1
2
AJ28
AK10
1
2
PEX_TX15
DACA_VSYNC
PCIE_GTX_C_MRX_N15
CARD_VGA_R
C40
1
2
0.1U_0402_10V7K
AH27
AH11
R15
1
2
150_0402_1%
PEX_TX15_N
DACA_RED
CARD_VGA_B
AH12
CARD_VGA_B <2>
DACA_BLUE
CLK_PCIE_VGA
A H14
AJ12
CARD_VGA_G
<2>
CLK_PCIE_VGA
PEX_REFCLK
DACA_GREEN
CLK_PCIE_VGA#
AJ14
AG9
<2>
CLK_PCIE_VGA#
PEX_REFCLK_N
DACA_IDUMP
DACA_RSET
R16
124_0603_1%
AH9
1
2
DACA_RSET
PLTRST_VGA#
1K_0402_1%
1
2
AH15
<2>
PLTRST_VGA#
PEX_RST_N
R89
DACAVREF
2
AH10
1
2
DACA_VREF
C41
0.01U_0402_16V7K
+3VS
C290
0.1U_0402_16V4Z
@
AM12
AG7
PEX_TSTCLK_OUT
DACC_HSYNC
B
B
AM11
AG5
PEX_TSTCLK_OUT_N
DACC_VSYNC
1
AF6
DACC_RED
AE5
DACC_BLUE
R17
10K_0402_5%
1
2
A26
AG6
TESTMEMCLK
DACC_GREEN
R18
10K_0402_5%
U14
1
2
H2
AG4
NVidia suggestion
2
TESTMODE
DACC_IDUMP
+3VS
AF5
7
5
DACC_RSET
VDD
REF
R85
1
2
@
10K_0402_5%
AJ11
0.1U_0402_16V4Z
C305
R287
JTAG_TCK
R86
@
10K_0402_5%
OSC_OUT
OSC_SPREAD
1
2
AK12
AH4
1
4
1
2
JTAG_TDI
DACC_VREF
1
XIN
MODOUT
AL12
JTAG_TDO
R87
@
10K_0402_5%
CARD_CRMA
@
22_0402_5%
1
2
AK11
R6
8
3
CARD_CRMA <2>
CARD_COMP <2>
CARD_LUMA <2>
JTAG_TMS
DACB_RED
XOUT
NC
R88
10K_0402_5%
CARD_COMPS
1
2
AL13
T6
JTAG_N
DACB_BLUE
CARD_LUMA
T5
2
6
DACB_GREEN
VSS
PD#
C43
IFPAB_VPROBE
IFPCD_VPROBE
1
2
AM4
V7
IFPAB_VPROBE
DACB_IDUMP
@
0.01U_0402_16V7K
DACB_RSET
R20
124_0603_1%
ASM3P1819N-SR_SO8
@
AK3
R7
1
2
IFPCD_VPROBE
DACB_RSET
C44
1
2
@
0.01U_0402_16V7K
DACBVREF
R5
1
2
DACB_VREF
XTALIN
XTALOUT
C45
0.01U_0402_16V7K
U1
XTALIN
CARD_DDCCLK
U2
K2
CARD_DDCCLK <2>
XTALOUT
I2CA_SCL
CARD_DDCDATA
J3
CARD_DDCDATA <2>
I2CA_SDA
T2
H4
XTALOUTBUFF
I2CB_SCL
DVI_DDCCLK <2>
DVI_DDCDAT <2>
+3VS
J4
I2CB_SDA
Y1
G2
EDID_CLK_LCD
I2CC_SCL
EDID_CLK_LCD <2>
EDID_DAT_LCD
4
3
T1
G1
EDID_DAT_LCD <2>
GND
OUT
XTALSSIN
I2CC_SDA
+3VS
G3
I2CH_SCL
I2CH_SCL
I2CH_SDA
1
2
H3
IN
GND
I2CH_SDA
U12
27MHZ_16PF_X7T027000BG1H-V
1
8
NC
VCC
G72M_BGA820
G72M@
DVI8X@
1
1
2
7
NC
NC
C47
22P_0402_50V8J
C48
22P_0402_50V8J
DVI_DDCCLK
DVI_DDCDAT
R279
4.7K_0402_5%
I2CH_SCL
I2CH_SDA
1
2
3
6
NC
SCL
R280
DVI8X@
4.7K_0402_5%
1
2
4
5
GND
SDA
R22
OSC_SPREAD
2
2
OSC_OUT
EDID_CLK_LCD
EDID_DAT_LCD
R284
2.2K_0402_5%
AT88SC0808C-SU-2.7_SO8
DVI8X@
1
2
1
2
A
22_0402_5%
R397
A
1
2
@
2.2K_0402_5%
R24
10K_0402_5%
R25
10K_0402_5%
R399
10K_0402_5%
DVI8X@
I2CH_SCL
1
2
I2CH_SDA
R398
1
2
10K_0402_5%
DVI8X@
Note: 4/17 modified Y1 pn to SJ100000780
Compal Secret Data
Compal Electronics, Inc.
Security Classification
2005/06/20
2006/06/20
Title
Issued Date
Deciphered Date
SCHEMATIC, VGA/B LS-354JP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Document Number
Rev
4059G1
B
B
Date:
݋ಂ六 ̬˜
14, 2007
Sheet
3
of
13
5
4
3
2
1
 
5
4
3
2
1
FBAD[0..63]
FBCD[0..63]
FBAD[0..63] <7,8>
FBCD[0..63] <9,10>
FBAA[0..12]
FBCA[0..12]
FBAA[0..12] <7,8>
FBCA[0..12] <9,10>
D
D
FBBA[2..5]
FBDA[2..5]
FBBA[2..5] <7,8>
FBDA[2..5] <9,10>
FBADQS[0..7]
FBCDQS[0..7]
FBADQS[0..7] <7,8>
FBCDQS[0..7] <9,10>
FBADQS#[0..7]
FBCDQS#[0..7]
FBADQS#[0..7]
<7,8>
FBCDQS#[0..7] <9,10>
FBADQM#[0..7]
FBCDQM#[0..7]
FBADQM#[0..7] <7,8>
FBCDQM#[0..7]
<9,10>
U1B
U1C
FBAD0
FBAA3
FBCD0
FBCA3
N27
P32
B7
C13
FBAD0
FBA_CMD0
FBCD0
FBC_CMD0
FBAD1
M27
Part 2 of 6
U27
FBAA0
FBCD1
A7
Part 3 of 6
A16
FBCA0
FBCA2
FBCA1
FBAD1
FBA_CMD1
FBCD1
FBC_CMD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAA2
FBCD2
FBCD3
FBCD4
FBCD5
N28
P31
C7
A13
FBAD2
FBA_CMD2
FBCD2
FBC_CMD2
FBAA1
L29
U30
A2
B17
FBAD3
FBA_CMD3
FBCD3
FBC_CMD3
FBBA3
FBBA4
FBDA3
FBDA4
K27
Y31
B2
B20
FBAD4
FBA_CMD4
FBCD4
FBC_CMD4
K28
W32
C4
A19
FBAD5
FBA_CMD5
FBCD5
FBC_CMD5
FBBA5
FBCD6
FBCD7
FBCD8
FBCD9
FBDA5
J29
W31
A5
B19
FBAD6
FBA_CMD6
FBCD6
FBC_CMD6
FBACS1#
FBCCS1#
J28
T32
B5
B14
FBAD7
FBA_CMD7
FBCD7
FBC_CMD7
FBACS0#
FBCCS0#
P30
V27
F9
E16
FBAD8
FBA_CMD8
FBACS0# <7,8>
FBAWE# <7,8>
FBA_BA0 <7,8>
FBCD8
FBC_CMD8
FBCCS0# <9,10>
FBCWE# <9,10>
FBC_BA0 <9,10>
FBAWE#
FBCWE#
FBC_BA0
N31
T28
F10
A14
FBAD9
FBA_CMD9
FBCD9
FBC_CMD9
FBA_BA0
FBCD10
N30
T31
D12
C15
FBAD10
FBA_CMD10
FBCD10
FBC_CMD10
FBAD11
FBA_CKE
FBCD11
FBC_CKE
N32
U32
D9
B16
FBA_CKE <7,8>
FBC_CKE <9,10>
FBAD11
FBA_CMD11
FBCD11
FBC_CMD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAODT0_R
FBBA2
FBAODT0
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCODT0_R
FBCODT0
L31
W29
1
2
E12
F17
1
2
FBAD12
FBA_CMD12
FBAODT0
<7,8>
FBCD12
FBC_CMD12
FBCODT0 <9,10>
7X@
0_0402_5%
FBDA2
7X@
0_0402_5%
R28
L30
W30
D11
C19
FBAD13
FBA_CMD13
FBCD13
FBC_CMD13
J30
T27
FBAA12
R27
R29
10K_0402_5%
E8
D15
FBCA12
FBAD14
FBA_CMD14
FBCD14
FBC_CMD14
FBARAS#
FBCRAS#
R30
10K_0402_5%
256@
L32
V28
D8
C17
FBARAS#
<7,8>
FBCRAS# <9,10>
FBAD15
FBA_CMD15
FBCD15
FBC_CMD15
H30
V30
FBAA11
FBAA10
E7
A17
FBCA11
FBAD16
FBA_CMD16
FBCD16
FBC_CMD16
C
FBAD17
FBAD18
FBAD19
R291
10K_0402_5%
FBCA10
C
K30
U31
F7
C16
FBAD17
FBA_CMD17
FBCD17
FBC_CMD17
FBA_BA1
FBC_BA1
R292
10K_0402_5%
256@
H31
R27
D6
D14
FBAD18
FBA_CMD18
FBA_BA1 <7,8>
FBCD18
FBC_CMD18
FBC_BA1 <9,10>
FBAA8
FBCD19
FBCA8
F30
V29
D5
F16
FBAD19
FBA_CMD19
FBCD19
FBC_CMD19
FBAD20
FBAA9
FBAA6
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCA9
FBCA6
FBCA5
H32
T30
D3
C14
FBAD20
FBA_CMD20
FBCD20
FBC_CMD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
E31
W28
E4
C18
FBAD21
FBA_CMD21
FBCD21
FBC_CMD21
FBAA5
D30
R29
C3
E14
FBAD22
FBA_CMD22
FBCD22
FBC_CMD22
FBAA7
FBCA7
FBCA4
E30
R30
B4
B13
FBAD23
FBA_CMD23
FBCD23
FBC_CMD23
FBAA4
H28
P29
C10
E15
FBAD24
FBA_CMD24
FBCD24
FBC_CMD24
FBACAS#
FBCCAS#
H29
U28
B10
F15
FBAD25
FBA_CMD25
FBACAS#
<7,8>
FBCD25
FBC_CMD25
FBCCAS# <9,10>
E29
Y32
C8
A20
FBAD26
FBA_CMD26
FBCD26
FBC_CMD26
J27
A10
FBAD27
FBCD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBADQM#0
FBADQM#1
FBADQM#3
FBCDQM#0
F27
M29
C11
A4
FBAD28
FBADQM0
FBCD28
FBCDQM0
E27
M30
C12
E11
FBCDQM#1
FBCDQM#2
FBAD29
FBADQM1
FBCD29
FBCDQM1
FBADQM#2
FBADQM#4
FBCD30
FBCD31
E28
G30
A11
F5
FBAD30
FBADQM2
FBCD30
FBCDQM2
FBCDQM#3
F28
F29
B11
C9
FBAD31
FBADQM3
FBCD31
FBCDQM3
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCDQM#4
FBCDQM#6
AD29
AA29
B28
C28
FBAD32
FBADQM4
FBCD32
FBCDQM4
FBADQM#5
FBCDQM#5
FBCDQM#7
A E29
AK30
C27
F24
FBAD33
FBADQM5
FBCD33
FBCDQM5
FBADQM#6
AD28
AC30
C26
C24
FBAD34
FBADQM6
FBCD34
FBCDQM6
FBADQM#7
AC28
AG30
B26
E20
FBAD35
FBADQM7
FBCD35
FBCDQM7
AB29
C30
FBAD36
FBCD36
FBADQS#0
FBADQS#1
FBADQS#2
FBADQS#3
FBADQS#4
FBADQS#5
FBADQS#6
FBADQS#7
FBCDQS#0
FBCDQS#1
FBCDQS#2
FBCDQS#3
FBCDQS#4
FBCDQS#5
FBCDQS#6
FBCDQS#7
AA30
M28
B31
C6
FBAD37
FBADQS_RN0
FBCD37
FBCDQS_RN0
FBAD38
FBAD39
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
Y28
K32
C29
E9
FBAD38
FBADQS_RN1
FBCD38
FBCDQS_RN1
AB30
G31
A31
E6
FBAD39
FBADQS_RN2
FBCD39
FBCDQS_RN2
FBAD40
A M30
G27
D28
A8
FBAD40
FBADQS_RN3
FBCD40
FBCDQS_RN3
FBAD41
FBAD42
AF30
AA28
D27
B29
FBAD41
FBADQS_RN4
FBCD41
FBCDQS_RN4
A J31
AL31
F26
E25
FBAD42
FBADQS_RN5
FBCD42
FBCDQS_RN5
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
AJ30
AF31
D24
A25
FBAD43
FBADQS_RN6
FBCD43
FBCDQS_RN6
A J32
AH29
E23
F21
FBAD44
FBADQS_RN7
FBCD44
FBCDQS_RN7
AK29
E26
FBAD45
FBCD45
+1.8VS
FBADQS0
FBCDQS0
A M31
L28
E24
C5
FBAD46
FBADQS_WP0
FBCD46
FBCDQS_WP0
+1.8VS
FBADQS1
FBADQS3
FBADQS4
FBADQS6
FBCDQS1
FBCDQS3
AL30
K31
F23
E10
FBAD47
FBADQS_WP1
FBCD47
FBCDQS_WP1
FBADQS2
FBCDQS2
AE32
G32
B23
E5
FBAD48
FBADQS_WP2
FBCD48
FBCDQS_WP2
B
B
AE30
G28
A23
B8
FBAD49
FBADQS_WP3
FBCD49
FBCDQS_WP3
FBCDQS4
R31
1K_0402_1%
AE31
AB28
C25
A29
FBAD50
FBADQS_WP4
FBCD50
FBCDQS_WP4
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBADQS5
FBADQS7
R32
1K_0402_1%
FBCDQS5
AD30
AL32
C23
D25
FBAD51
FBADQS_WP5
FBCD51
FBCDQS_WP5
FBCDQS6
FBCDQS7
AC31
AF32
A22
B25
FBAD52
FBADQS_WP6
FBCD52
FBCDQS_WP6
A C32
AH30
C22
F20
FBAD53
FBADQS_WP7
FBCD53
FBCDQS_WP7
AB32
C21
FBAD54
FBCD54
A B31
E32
FB_VREF1
15mil
B22
A28
FB_VREF2
15mil
FBAD55
FB_VREF1
FBCD55
FB_VREF2
AG27
E22
FBAD56
FBCD56
A F28
P28
FBACLK0
D22
E13
FBCCLK0
FBCCLK0#
FBCCLK1
FBCCLK1#
1
FBAD57
FBA_CLK0
FBACLK0 <7>
FBACLK0# <7>
FBACLK1 <8>
FBACLK1# <8>
FBCD57
FBC_CLK0
FBCCLK0 <9>
FBCCLK0# <9>
FBCCLK1 <10>
FBCCLK1# <10>
FBACLK0#
C50
0.1U_0402_16V4Z
R33
1K_0402_1%
AH28
R28
D21
F13
1
FBAD58
FBA_CLK0_N
FBCD58
FBC_CLK0_N
FBAD59
FBACLK1
FBACLK1#
FBCD59
FBCD60
FBCD61
C51
0.1U_0402_16V4Z
R34
1K_0402_1%
A G28
Y27
E21
F18
FBAD59
FBA_CLK1
FBCD59
FBC_CLK1
FBAD60
FBAD61
AG29
AA27
E18
E17
FBAD60
FBA_CLK1_N
2
FBCD60
FBC_CLK1_N
R282
A D27
D32
D19
B1
1
2
FBAD61
FBA_REFCLK
FBCD61
FBC_REFCLK
2
FBAD62
FBAD63
FBCD62
FBCD63
R283
@
0_0402_5%
AF27
D31
D18
C1
1
2
FBAD62
FBA_REFCLK_N
FBCD62
FBC_REFCLK_N
FBA_DEBUG
FBC_DEBUG
@
0_0402_5%
AE28
AC27
E19
F12
FBAD63
FBA_DEBUG
FBCD63
FBC_DEBUG
R400
FBAODT0
1
2
G72M_BGA820
G72M@
0_0402_5%
G72M_BGA820
G72M@
R401
FBCODT0
1
2
8X@
FB_VREF1=0.5 x FBVDD
0_0402_5%
SMB_DAT
<2>
FB_VREF2=0.5 x FBVDD
8X@
SMB_CLK
<2>
follow
PUN-02736-001, HW1
PUN-02737-001
A
A
Compal Secret Data
Compal Electronics, Inc.
Security Classification
2005/06/20
2006/06/20
Title
Issued Date
Deciphered Date
SCHEMATIC, VGA/B LS-354JP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Document Number
Rev
4059G1
Custom
B
Date:
݋ಂ六 ̬˜
14, 2007
Sheet
4
of
13
5
4
3
2
1
 
5
4
3
2
1
+VGA_CORE
+1.2VS
R406
1420mA
1
2
0_0402_5%
8X@
MAX. 20A
0.022U_0402_16V7K
1
0.022U_0402_16V7K
1
+VGA_CORE
U1E
1
1
1
+1.2VS
MBK1608121YZF_0603
7X@
2.2U_0603_6.3V6K
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1
C54
C55
C56
C57
C58
K16
AD23
VDD_0
PEX_IOVDD_0
Part 5 of 6
K17
AF23
VDD_1
PEX_IOVDD_1
NV_PLLVDD
0.022U_0402_16V7K
1
2
N13
AF24
1
1
1
VDD_2
PEX_IOVDD_2
2
2
2
2
2
8mA
C59
C60
C61
C62
C63
C64
N14
AF25
VDD_3
PEX_IOVDD_3
L1
N16
AG24
1
1
VDD_4
PEX_IOVDD_4
D
C52
C53
0.022U_0402_16V7K
0.022U_0402_16V7K
D
N17
AG25
2
2
2
2
2
2
VDD_5
PEX_IOVDD_5
N19
VDD_6
0.1U_0402_16V4Z
N20
AC16
2
2
VDD_7
PEX_IOVDDQ_0
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
P13
AC17
VDD_8
PEX_IOVDDQ_1
0.01U_0402_16V7K
1
2.2U_0603_6.3V6K
1
2.2U_0603_6.3V6K
1
P14
AC21
VDD_9
PEX_IOVDDQ_2
P16
AC22
1
1
1
1
VDD_10
PEX_IOVDDQ_3
C67
C68
C69
C70
C71
C72
C73
P17
AE18
VDD_11
PEX_IOVDDQ_4
+1.2VS
MBK1608121YZF_0603
8X@
P19
AE21
VDD_12
PEX_IOVDDQ_5
L14
Co-layout G7X NV8X
R16
AE22
VDD_13
PEX_IOVDDQ_6
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1
1
2
R17
AF12
+2.5VS
VDD_14
PEX_IOVDDQ_7
NV_PLLVDD
T13
AF18
VDD_15
PEX_IOVDDQ_8
MBK1608121YZF_0603
7X@
2.2U_0603_6.3V6K
1
1
1
T14
AF21
VDD_16
PEX_IOVDDQ_9
4700P_0402_25V7K
1
VID_PLLVDD
C77
C78
C79
C80
C81
C82
0.01U_0402_16V7K
0.01U_0402_16V7K
2.2U_0603_6.3V6K
+1.2VS
1
2
T15
AF22
VDD_17
PEX_IOVDDQ_10
L2
40mA
L3
T18
VDD_18
T19
AF15
+PEX_PLLAVDD
+PEX_PLLDVDD
100mA
1
2
1
VDD_19
PEX_PLLAVDD
2
2
2
2
2
2
C74
C75
20mA
U13
AE15
VDD_20
PEX_PLLDVDD
+3VS
U14
10NH_LQG15HS10NJ02D_5%_0402
1
1
VDD_21
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C83
C84
U15
M7
2
2
VDD_22
MIOA_VDDQ_0
+1.8VS
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
1
U19
M8
VDD_23
MIOA_VDDQ_1
L5
V16
R8
1
VDD_24
MIOA_VDDQ_2
2
2
C85
C86
2.2U_0603_6.3V6K
V17
T8
VDD_25
MIOA_VDDQ_3
+1.2VS
MBK1608121YZF_0603
8X@
1U_0402_6.3V4Z
1
0.47U_0402_6.3V6K
1
4700P_0402_25V7K
1
0.1U_0402_16V4Z
W13
U9
1
2
VDD_26
MIOA_VDDQ_4
L6
L15
MBK1608121YZF_0603
W14
AA8
VDD_27
MIOB_VDDQ_0
2
2
Co-layout G7X NV8X
1
2
W16
AB7
1
2
1
1
1
1
VDD_28
MIOB_VDDQ_1
+2.5VS
MBK1608121YZF_0603
7X@
C90
C91
C92
C93
0.1U_0402_16V4Z
C94
C95
C96
W17
AB8
VDD_29
MIOB_VDDQ_2
10NH_LQG15HS10NJ02D_5%_0402
W19
AC6
1
1
VDD_30
MIOB_VDDQ_3
PLLVDD
C97
C98
1
2
Y13
AC7
2
2
2
2
VDD_31
MIOB_VDDQ_4
2
2
2
30mA
L4
4700P_0402_25V7K
1
Y14
L1
2.2U_0603_6.3V6K
VDD_32
MIOACAL_PD_VDDQ
1
Y16
Y1
VDD_33
MIOBCAL_PD_VDDQ
2
2
+1.8VS
C87
0.47U_0402_6.3V6K
0.47U_0402_6.3V6K
Y17
470P_0402_50V7K
2.2U_0603_6.3V6K
VDD_34
C88
130mA
130mA
IFPA_IOVDD
L16
MBK1608121YZF_0603
0.1U_0402_16V4Z
Y19
AF9
VDD_35
IFPA_IOVDD
Y20
AF8
8X@
1
VDD_36
IFPB_IOVDD
2
+2.5VS
C
2.2U_0603_6.3V6K
150mA
150mA
IFPC_IOVDD
C
U18
AD6
1
2
2
2
VDD_37
IFPC_IOVDD
IFPD_IOVDD
R41
10K_0402_5%
L8
AE7
1
2
IFPD_IOVDD
1U_0402_6.3V4Z
R42
10K_0402_5%
Co-layout G7X NV8X
P20
VDD_LP_0
35mA
IFPAB_CD_PLLVDD
4700P_0402_25V7K
1
1
T20
AC9
1
2
VDD_LP_1
IFPAB_PLLVDD
C101
35mA
MBK1608121YZF_0603
7X@
T23
AA10
1
2
1
1
VDD_LP_2
IFPCD_PLLVDD
R93
10K_0402_5%
C105
C106
C107
MAX. 130mA
U20
VDD_LP_3
135mA
200mA
DACA_VDD
U23
AD10
VDD_LP_4
DACA_VDD
2
200mA
DACB_VDD
W20
V8
VDD_LP_5
DACB_VDD
2
2
2
+3VS
DACC_VDD
AD7
2.2U_0603_6.3V6K
DACC_VDD
+1.2VS
MBK1608121YZF_0603
470P_0402_50V7K
0.47U_0402_6.3V6K
1
0.022U_0402_16V7K
1
2.2U_0603_6.3V6K
1
H7
A3
VDD33_0
FBVDD_0
FBA_PLLAVDD
1
2
1
1
1
J7
A6
VDD33_1
FBVDD_1
C108
C109
C110
C111
C112
C113
K7
A9
VDD33_2
FBVDD_2
L7
R43
10K_0402_5%
L7
A12
1
1
VDD33_3
FBVDD_3
C99
C100
Not Supports TMDS
L8
A15
VDD33_4
FBVDD_4
2
2
2
2
2
2
+3VS
L17
L10
A18
VDD33_5
FBVDD_5
0.47U_0402_6.3V6K
0.022U_0402_16V7K
0.022U_0402_16V7K
DVI8X@
1
M10
A21
2
2
VDD33_6
FBVDD_6
2.2U_0603_6.3V6K
IFPC_IOVDD
AC11
A24
2
VDD33_7
FBVDD_7
4700P_0402_25V7K
DVI8X@ 1
AC12
A27
VDD33_8
FBVDD_8
4700P_0402_25V7K
0.1U_0402_16V4Z
1
MBK1608121YZF_0603
AC24
A30
1
VDD33_9
FBVDD_9
+1.8VS
L18
MBK1608121YZF_0603
C298
C299
1
1
AD24
C32
VDD33_10
FBVDD_10
C116
C117
C118
DVI8X@
1
AE11
F32
VDD33_11
FBVDD_11
AE12
J32
2
VDD33_12
FBVDD_12
2
2
M32
4700P_0402_25V7K
DVI8X@ 1
2.2U_0603_6.3V6K
DVI8X@
FBVDD_13
2
2
2
2.2U_0603_6.3V6K
VID_PLLVDD
40mA
30mA
T10
R32
1
VID_PLLVDD
FBVDD_14
+1.2VS
0.1U_0402_16V4Z
PLLVDD
T9
V32
C301
C302
PLLVDD
FBVDD_15
MBK1608121YZF_0603
AA32
FBVDD_16
FBC_PLLAVDD
1
2
AD32
FBVDD_17
2
2
L9
FBA_PLLAVDD
30mA
30mA
NC For G7xM
2.2U_0603_6.3V6K
DVI8X@
G25
AG32
FBA_PLLAVDD
FBVDD_18
FBC_PLLAVDD
NV8X DVI option
1
1
G10
AK32
FBC_PLLAVDD
FBVDD_19
+1.8VS
C114
2.2U_0603_6.3V6K
C115
H_PLLVDD
15mA
G23
FBA_PLLVDD
G8
G11
+1.8VS
FBC_PLLVDD
FBVDDQ_0
B
R44
B
1
2
K26
G12
FBCAL_PD_VDDQ
FBVDDQ_1
2
2
NA
40.2_0402_1%
MAX. 3.8A
G15
FBVDDQ_2
2.2U_0603_6.3V6K
1
0.01U_0402_16V7K
1
0.01U_0402_16V7K
1
+1.8VS
H16
G18
FBVTT_0
FBVDDQ_3
4700P_0402_25V7K
1
1
H17
G21
FBVTT_1
FBVDDQ_4
C122
C123
C124
C126
C127
4700P_0402_25V7K
1
4700P_0402_25V7K
1
4700P_0402_25V7K
1
0.022U_0402_16V7K
1
2.2U_0603_6.3V6K
1
J9
G22
FBVTT_2
FBVDDQ_5
J10
H11
1
1
1
1
1
FBVTT_3
FBVDDQ_6
J23
H12
C130
C131
C132
C133
C134
C135
C136
C137
C138
C139
FBVTT_4
FBVDDQ_7
2
2
2
2
2
J24
H15
FBVTT_5
FBVDDQ_8
0.1U_0402_16V4Z
0.01U_0402_16V7K
K9
H18
FBVTT_6
FBVDDQ_9
2
2
2
2
2
2
2
2
2
2
K11
H21
FBVTT_7
FBVDDQ_10
K12
L25
FBVTT_8
FBVDDQ_11
4700P_0402_25V7K
4700P_0402_25V7K
0.022U_0402_16V7K
0.022U_0402_16V7K
2.2U_0603_6.3V6K
K21
L26
FBVTT_9
FBVDDQ_12
K22
M25
FBVTT_10
FBVDDQ_13
K24
M26
FBVTT_11
FBVDDQ_14
MBK1608121YZF_0603
1
0.022U_0402_16V7K
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1
L23
R25
FBVTT_12
FBVDDQ_15
4700P_0402_25V7K
1
DACA_VDD
2
M23
R26
+3VS
1
1
1
1
1
FBVTT_13
FBVDDQ_16
L12
C140
C141
C142
C143
C144
C145
C146
C147
C148
T25
V25
FBVTT_14
FBVDDQ_17
U25
V26
1
1
FBVTT_15
FBVDDQ_18
C149
2.2U_0603_6.3V6K
C150
C151
AA23
AA25
FBVTT_16
FBVDDQ_19
2
2
2
2
2
2
2
2
2
AB23
AA26
FBVTT_17
FBVDDQ_20
0.022U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AB25
2
2
2
FBVDDQ_21
AB26
FBVDDQ_22
F6
H22
NC
FBVDDQ_23
470P_0402_50V7K
+1.2VS
8X@
L13
MBK1608121YZF_0603
G72M_BGA820
G72M@
MBK1608121YZF_0603
Co-layout G7X NV8X
+1.8VS
H_PLLVDD
1
2
+VGA_CORE
L19
4700P_0402_25V7K
1
DACB_VDD
1
2
1
1
C294
2.2U_0603_6.3V6K
8X@
C295
1
1
1
1
C152
2.2U_0603_6.3V6K
C153
C154
C155
330U_D2E_2.5VM
+ C156
330U_D2E_2.5VM
2.2U_0603_6.3V6K
1
2.2U_0603_6.3V6K
1
1
2
2
A
+
A
+
C292
330U_D2E_2.5VM
C306
C307
2
2
2
4700P_0402_25V7K
8X@
2
2
2
2
2
470P_0402_50V7K
Average to place around +VGA_CORE
plane.
Compal Secret Data
Compal Electronics, Inc.
Security Classification
2005/06/20
2006/06/20
Title
Issued Date
Deciphered Date
SCHEMATIC, VGA/B LS-354JP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Document Number
Rev
4059G1
B
B
Date:
݋ಂ六 ̬˜
14, 2007
Sheet
5
of
13
5
4
3
2
1
 

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