EMIF03-SIM02F2.pdf

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3 LINES EMI FILTER INCLUDING ESD PROTECTION
®
EMIF03-SIM02F2
IPAD™
3 LINE EMI FILTER
INCLUDING ESD PROTECTION
MAIN PRODUCT APPLICATIONS:
EMI filtering and ESD protection for:
■ SIM Interface (Subscriber Identify Module)
■ UIM Interface (Universal Identify Module)
DESCRIPTION
The EMIF03-SIM02F2 is a highly integrated
device designed to suppress EMI/RFI noise in all
systems subjected to electromagnetic interfer-
ence. The EMIF03 flip chip packaging means the
package size is equal to the die size.
This filter includes an ESD protection circuitry
which prevents the device from destruction when
subjected to ESD surges up 15kV.
BENEFITS
■
Flip-Chip
(8 Bumps)
EMI symmetrical (I/O) low-pass filter
Table 1: Order Code
Part Number
Marking
High efficiency in EMI filtering
■
EMIF03-SIM02F2
GJ
Lead free package
■
Very low PCB space consuming:
1.42mm x 1.42mm
■
Figure 1: Pin Configuration (Ball side)
Very thin package: 0.65 mm
■
High efficiency in ESD suppression
■ High reliability offered by monolithic integration
■ High reducing of parasitic elements through
integration & wafer level packaging.
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2
Level 4 on external & V cc pins:
15kV(air discharge)
8kV (contact discharge)
Level 1 on internal pins: 2kV (air discharge)
2kV (contact discharge)
MIL STD 883E - Method 3015-6 Class 3
■
3
2
1
RST
in
RST
ext
A
CLK
in
Gnd
CLK
ext
B
Data
in
V CC
Data
ext
C
Figure 2: Configuration
V CC
100 Ω
RST in
R1
RST ext
47
Ω
CLK in
CLK ext
R2
100 Ω
Data in
Data ext
R3
Cline = 20pF max.
GND
TM: IPAD is a trademark of STMicroelectronics.
September 2005
REV. 5
1/7
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EMIF03-SIM02F2
Table 2: Absolute Ratings (limiting values)
Symbol
Parameter and test conditions
Value
Unit
V PP
Internal pins (A3, B3, C3):
ESD discharge IEC61000-4-2, air discharge
ESD discharge IEC61000-4-2, contact discharge
External pins (A2, B1, C2, C1):
ESD discharge IEC61000-4-2, air discharge
ESD discharge IEC61000-4-2, contact discharge
2
2
kV
15
8
T j
Maximum junction temperature
125
°C
T op
Operating temperature range
- 40 to + 85
°C
T stg
Storage temperature range
- 55 to + 150
°C
Table 3: Electrical Characteristics (T amb = 25°C)
Symbol Parameter
V BR Breakdown voltage
I RM Leakage current @ V RM
V RM Stand-off voltage
V CL Clamping voltage
R d Dynamic impedance
I PP Peak pulse current
R I/O Series resistance between Input &
Output
C line Input capacitance per line
I
I F
V CL
V BR
V RM
V F
V
I RM
I R
I PP
Symbol
Test conditions
Min.
Typ.
Max.
Unit
V BR
I R = 1 mA
6
20
V
I RM
V RM = 3V
0.2
µA
R d
1.5
Ω
R 1 , R 3 Tolerance ± 20%
100
Ω
R 2
Tolerance ± 20%
47
Ω
C line
@ 0V
20
pF
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438464384.002.png 438464384.003.png
EMIF03-SIM02F2
Figure 3: S21 (dB) attenuation measurement
(A2-A3 line)
Figure 4: S21 (dB) attenuation measurement
(B1-B3 line)
0.00
EMIF03-SIM02F2_FREQ-MEAS_PM428
Aplac 7.70 User: ST Microelectronics Sep 22 2004
0.00
EMIF03-SIM02F2_FREQ-MEAS_PM428
Aplac 7.70 User: ST Microelectronics Sep 22 2004
dB
dB
-10.00
-10.00
-20.00
-20.00
-30.00
-30.00
-40.00
-40.00
100.0k
1.0M
10.0M
100.0M
1.0G
100.0k
1.0M
10.0M
100.0M
1.0G
f/Hz
f/Hz
A2/A3 Line
B1/B3 line
Figure 5: S21 (dB) attenuation measurement
(C1-C3 line)
Figure 6: Analog crosstalk measurements
EMIF03-SIM02F2_FREQ-MEAS_PM428
Aplac 7.70 User: ST Microelectronics Sep 22 2004
EMIF03-SIM02F2_FREQ-MEAS_PM428
Aplac 7.70 User: ST Microelectronics Sep 22 2004
0.00
0.00
dB
dB
-10.00
-20.00
-10.00
-30.00
-40.00
-20.00
-50.00
-60.00
-70.00
-30.00
-80.00
-90.00
-40.00
-100.00
100.0k
1.0M
10.0M
100.0M
1.0G
100.0k
1.0M
10.0M
100.0M
1.0G
f/Hz
f/Hz
C1/C3 line
Xtalk A2/B3
Figure 7: Voltages when IEC61000-4-2 (+15 kV
air discharge) applied to external pin
Figure 8: Voltages when IEC61000-4-2 (-15 kV
air discharge) applied to external pin
Vexternal : 10V/d
Vexternal : 5V/d
Vinternal : 10V/d
Vinternal : 5V/d
100ns/d
100ns/d
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438464384.004.png
EMIF03-SIM02F2
Figure 9: Line capacitance versus reverse
applied voltage (typical)
C(pF)
20.00
16.00
12.00
8.00
4.00
VR(V)
0.00
0
1
2
3
4
5
Figure 10: Aplac model
LbumpRbump
100
Rbump
Lbump
a3
a2
Cbump
Rsub
Rsub Cbump
bulk
bulk
Lbump Rbump
47
Rbump
Lbump
b3
b1
Cbump
Rsub
Rsub Cbump
bulk
bulk
Lbump Rbump
100
Rbump
Lbump
c1
c3
Rsub
bulk
Dext2
Dint1
Dint1
bulk
Cbump
Dext1
Dext1
Dint2
Rsub Cbump
0.25
0.28
0.25
0.29 0.31
0.29
Bulk
Lbump
Ls 100m
Rbump
100m Ls
a2
a3
Lgnd
Cgnd
Port1
Port2
50
50
Rgnd
Figure 11: Aplac parameters
Ls 950pH
Rs 150m
Cext1 15pF
Cint1 4.5pF
Cext2 14pF
Cint2 4pF
Rbump 20m
Lbump 50pH
Cbump 0.15pF
Rgnd 500m
Lgnd 50pH
Cgnd 0.15pF
Rsub 100m
Model Dint1
BV=15
CJO=Cint1
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.001m
VJ=0.6
TT=50n
Model Dext1
BV=15
CJO=Cext1
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.001m
VJ=0.6
TT=50n
Model Dint2
BV=15
CJO=Cint2
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.001m
VJ=0.6
TT=50n
Model Dext2
BV=15
CJO=Cext2
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.001m
VJ=0.6
TT=50n
4/7
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EMIF03-SIM02F2
Figure 12: Ordering Information Scheme
EMIF yy - xxx zz Fx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip-Chip
x = 1: 500µm, Bump = 315µm
= 2: Leadfree Pitch = 500µm, Bump = 315µm
= 3: Leadfree Pitch = 400µm, Bump = 250µm
Figure 13: FLIP-CHIP Package Mechanical Data
500µm ± 50
650µm ± 65
315µm ± 50
1.42mm ± 50µm
Figure 14: Foot print recommendations
Figure 15: Marking
3 65
240
Dot, ST logo
xx = marking
Copper pad Diameter :
250µm recommended , 300µm max
z = packaging
location
yww = datecode
(y = year
ww = week)
E
Solder stencil opening : 330µm
Solder mask opening recommendation :
340µm min for 315µm copper pad diameter
x
y
x
w
z
w
All dimensions in µm
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