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Dual AND-OR gate
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
·
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC58
Dual AND-OR gate
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Dual AND-OR gate
74HC58
FEATURES
·
Output capability: standard
·
I
CC
category: SSI
GENERAL DESCRIPTION
The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard no. 7A.
The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and
the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 15
°
C; t
r
= t
f
= 6 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
t
PHL
/ t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
1n to 1Y
11
ns
2n to 2Y
9
ns
C
I
input capacitance
3.5
pF
C
PD
power dissipation capacitance per
gate
notes 1 and 2
18
pF
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
m
W):
P
D
= C
PD
´
V
CC
2
´
f
i
+
å
(C
L
´
V
CC
2
´
f
o
) where:
f
o
) = sum of outputs
2. For HC the condition is V
I
= GND to V
CC
f
i
= input frequency in MHz
f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
å
(C
L
´
V
CC
2
´
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
December 1990
2
Philips Semiconductors
Product specification
Dual AND-OR gate
74HC58
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 12, 13, 9, 10, 11
1A to 1F
data inputs
2, 3, 4, 5
2A to 2D
data inputs
8, 6
1Y, 2Y
data outputs
7
GND
ground (0 V)
14
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual AND-OR gate
74HC58
Fig.4 Functional diagram.
Fig.5 Logic diagram.
FUNCTION TABLE
(1)
INPUTS
OUTPUT
INPUTS
OUTPUT
1A 1B 1C 1D
1E
1F
1Y
2A
2B
2C
2D
2Y
L
L
L
X
X
X
X
X
L
L
X
X
X
X
X
L
X
X
L
X
X
L
X
X
L
X
X
L
X
X
L
L
L
L
L
L
L
X
X
X
H
X
X
L
L
X
H
L
X
L
X
H
X
X
L
X
L
H
X
L
L
L
L
H
H
X
X
X
X
X
H
L
X
X
X
X
H
X
L
L
L
X
H
X
L
X
X
H
X
X
X
L
X
H
X
L
X
X
L
H
X
L
L
L
L
H
H
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
December 1990
4
Philips Semiconductors
Product specification
Dual AND-OR gate
74HC58
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
I
CC
category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(
°
C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
V
CC
(V)
+25
-
40 to +85
-
40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
1A,1B,1C,1D,1E,
1F to 1Y
36
13
10
115
23
20
145
29
25
175
35
30
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
2A,2B,2C,2D to 2Y
30
11
9
100
20
17
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.6
t
THL
/ t
TLH
output transition
time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
AC WAVEFORMS
handbook, full pagewidth
nA, nB, nC, nD,
1E, 1F INPUT
V
M
(1)
t
PHL
t
PLH
nY OUTPUT
V
M
(1)
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
MBA336
t
THL
t
TLH
Fig.6 Waveforms showing the input (nA, nB, nC, nD, 1E, 1F) to output (nY) propagation delays and the output
transition times.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990
5
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