74HC_HCT195_CNV_2.pdf

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4-bit parallel access shift register
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
·
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT195
4-bit parallel access shift register
Product specification
File under Integrated Circuits, IC06
December 1990
21701136.006.png
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
FEATURES
by the state of the parallel load enable (PE) inp u t. Serial
data enter s th e first flip-flop (Q 0 ) via the J and K inputs
when the PE input is HIGH and shifted one bit in the
direction Q 0 ® Q 1 ® Q 2 ® Q 3 following ea ch
LOW-to-HIGH clock tra nsition. The J and K inputs provide
the flexibility of the JK type input for special applications
and by tying the pins together, the simple D-type input for
general applications. The “19 5” a ppears as four common
clocked D flip-flops when the PE input is LOW.
After the LOW-to-HIGH clock transition, data on the
parallel inputs (D 0 to D 3 ) is transferred to the respective
Q 0 to Q 3 outputs. Shift left operation (Q 3 ®
·
As y nchronous master reset
·
J, K, (D) inputs to the first stage
·
Fully synchronous serial or parallel data transfer
·
Shift right and parallel load capability
·
Complement output from the last stage
·
Output capability: standard
·
I CC category: MSI
GENERAL DESCRIPTION
Q 2 ) can be
achieved b y ty ing the Q n outputs to the D n-1 inputs and
holding the PE input LOW.
All parallel and serial data transfers are synchronous,
occurring after each LOW-to-HIGH clock tran sit ion.
The re is no restriction on the activity of the J, K, D n and
PE inputs for logic operation other than the set-up and
hold time requ ire ments. A LOW on the asynchronous
master reset (MR) input sets all Q outputs LOW,
independent of any other input condition.
The 74HC/HCT195 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT195 performs serial, parallel,
serial-to-parallel or parallel-to-serial data transfer at very
high speeds. The “195” operates on two primary modes:
shift right (Q o ®
Q 1 ) and parallel load, which are controlled
QUICK REFERENCE DATA
GND = 0 V; T amb = 25 ° C; t r = t f = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
t PHL / t PLH
propagation delay CP to Q n
C L = 15 pF; V CC = 5 V
15
15
ns
f max
maximum clock frequency
57
57
MHz
C I
input capacitance
3.5
3.5
pF
C PD
power dissipation capacitance per package
notes 1 and 2
105
105
pF
Notes
1. C PD is used to determine the dynamic power dissipation (P D in m W):
P D = C PD ´
V CC 2
´
f i +å
(C L ´
V CC 2
´
f o ) where:
f i = input frequency in MHz
f o = output frequency in MHz
å
f o ) = sum of outputs
C L = output load capacitance in pF
V CC = supply voltage in V
2. For HC the condition is V I = GND to V CC
For HCT the condition is V I = GND to V CC - 1,5 V
(C L ´
V CC 2
´
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information” .
December 1990
2
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Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
MR
master reset input (active LOW)
2
J
first stage J- input (active HIGH)
3
K
first stage K-input (active LOW)
4, 5, 6, 7
D 0 to D 3
parallel data inputs
8
GN D
ground (0 V)
9
PE
parallel enable input (active LOW)
10
C P
clock input (LOW-to-HIGH edge-triggered)
11
Q 3
inverted output from the last stage
15, 14, 13, 12 Q 0 to Q 3
parallel outputs
16
V CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
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21701136.008.png 21701136.001.png 21701136.002.png 21701136.003.png
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
Fig.4 Functional diagram.
APPLICATIONS
·
Serial data transfer
·
Parallel data transfer
·
Serial-to-parallel data transfer
·
Parallel-to-serial data transfer
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODES
MR
CP
PE
J
K n 0 1 2 3 3
asynchronous reset
L
X
X
X
X
X
L
L
L
L
H
shift, set first stage
shift, reset first stage
shift, toggle first stage
shift, retain first stage
H
H
H
H
­
­
­
­
h
h
h
h
h
l
h
l
h
l
l
h
X
X
X
X
H
L
q0
q0
q0
q0
q0
q0
q1
q1
q1
q1
q2
q2
q2
q2
q 2
q 2
q 2
q2
parallel load
H
­
l
X
X
d n
d 0
d 1
d 2
d 3
d 3
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q, d = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the
LOW-to-HIGH clock transition
X = don’t care
­
= LOW-to-HIGH clock transition
December 1990
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Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
Fig.5 Logic diagram.
December 1990
5
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