74HC_HCT280_CNV_2.pdf

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT280

9-bit odd/even parity

generator/checker

Product speciﬁcation

File under Integrated Circuits, IC06

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit odd/even parity generator/checker

74HC/HCT280

FEATURES

transmission or data retrieval systems. Both even and odd

parity outputs are available for generating or checking

even or odd parity up to 9 bits.

Word-length easily expanded by cascading

Similar pin configuration to the “180” for easy system

up-grading

The even parity output ( å E ) is HIGH when an even number

of data inputs (I 0 to I 8 ) are HIGH. The odd parity output (

å 0 )

is HIGH when an odd number of data inputs are HIGH.

Generates either odd or even parity for nine data bits

Output capability: standard

Expansion to larger word sizes is accomplished by tying

the even outputs ( å E ) of up to nine parallel devices to the

data inputs of the final stage. For a single-chip 16-bit

even/odd parity generator/checker, see

PC74HC/HCT7080.

I CC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT280 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

APPLICATIONS

25-line parity generator/checker

The 74HC/HCT280 are 9-bit parity generators or checkers

commonly used to detect errors in high-speed data

81-line parity generator/checker

QUICK REFERENCE DATA

GND = 0 V; T amb =25

C; t r =t f = 6 ns

TYPICAL

SYMBOL PARAMETER

CONDITIONS

UNIT

HCT

t PHL / t PLH propagation delay

C L = 15 pF; V CC =5 V

I n to

å E

I n to

å O

C I

input capacitance

3.5

C PD

power dissipationcapacitance per package notes 1 and 2

Notes

1. C PD is used to determine the dynamic power dissipation (P D in

W):

P D =C PD ´

V CC 2

f i +å

(C L ´

V CC 2

f o ) where:

f o ) = sum of outputs

C L = output load capacitance in pF

V CC = supply voltage in V

2. For HC the condition is V I = GND to V CC

For HCT the condition is V I = GND to V CC - 1.5 V

f i = input frequency in MHz

f o = output frequency in MHz

(C L ´

V CC 2

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information” .

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit odd/even parity generator/checker

74HC/HCT280

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

8, 9, 10, 11, 12, 13, 1, 2, 4

I 0 to I 8

data inputs

5, 6

å E ,

å O

parity outputs

GND

ground (0 V)

V CC

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit odd/even parity generator/checker

74HC/HCT280

FUNCTION TABLE

INPUTS

OUTPUTS

number of HIGH data

inputs (I 0 to I 8 )

å E

å O

even

odd

Note

1. H = HIGH voltage level

L = LOW voltage level

Fig.4 Functional diagram.

Fig.5 Logic diagram.

December 1990

Philips Semiconductors

Product speciﬁcation

9-bit odd/even parity generator/checker

74HC/HCT280

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” .

Out put capability: standard

I CC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t r =t f = 6 ns; C L = 50 pF

T amb (

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

WAVEFORMS

V CC

(V)

40 to

125

min. typ. max. min. max. min. max.

t PHL / t PLH propagation delay

I n to

200

250

300

2.0

4.5

6.0

Fig.6

å E

t PHL / t PLH propagation delay

I n to

200

250

300

2.0

4.5

6.0

Fig.6

å O

t THL / t TLH output transition time

110

2.0

4.5

6.0

Fig.6

December 1990

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika: