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EMI FILTER INCLUDING ESD PROTECTION
®
EMIF10-1K010F2
IPAD™
EMI FILTER
INCLUDING ESD PROTECTION
MAIN PRODUCT CHARACTERISTICS:
Where EMI filtering in ESD sensitive equipment is
required
■ Mobile phones and communication systems
■ Computers, printers and MCU Boards
DESCRIPTION
The EMIF10-1K010F2 is a highly integrated
devices designed to suppress EMI/RFI noise in all
systems subjected to electromagnetic
interferences. The EMIF10 flip chip packaging
means the package size is equal to the die size.
This filter includes an ESD protection circuitry
which prevents the device from destruction when
subjected to ESD surges up 15kV.
Flip-Chip
(24 Bumps)
Table 1: Order Code
Part Number
Marking
BENEFITS
EMIF10-1K010F2
FD
■
EMI symmetrical (I/O) low-pass filter
■
High efficiency in EMI filtering
Figure 1: Pin Configuration (ball side)
Lead free package
■
■
Very low PCB space consuming:
2.57 mm x 2.57 mm
5
4
3
2
1
■
Very thin package: 0.65 mm
I7
GND GND
I3
A
High efficiency in ESD suppression
■
High reliability offered by monolithic integration
■ High reducing of parasitic elements through
integration & wafer level packaging.
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2
Level 4 15kV (air discharge)
8kV (contact discharge)
MIL STD 883E -Method 3015-6 Class 3
■
I9
GND GND
I5
I1
B
I10
I8
I6
I4
I2
C
09
07
05
03
01
D
010
08
06
04
02
E
Figure 2: Basic Cell Configuration
Low-pass Filter
Input
Output
Ri/o = 1k
Cline = 100pF
Ω
GND
GND
GND
TM: IPAD is a trademark of STMicroelectronics.
October 2004
REV. 1
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EMIF10-1K010F2
Table 2: Absolute Maximum Ratings (T amb = 25°C)
Symbol
Parameter and test conditions
Value
Unit
T j
Junction temperature
125
°C
T op
Operating temperature range
- 40 to + 85
°C
T stg
Storage temperature range
- 55 to + 150
°C
Table 3: Electrical Characteristics (T amb = 25°C)
Symbol Parameters
V BR Breakdown voltage
I RM Leakage current @ V RM
V RM Stand-off voltage
V CL
I
Clamping voltage
V CL
V BR
V RM
V
I
R d
Dynamic impedance
RM
I
I PP
Peak pulse current
R I/O
Series resistance between Input &
Output
PP
C in
Input capacitance per line
Symbol
Test conditions
Min.
Typ.
Max.
Unit
V BR
I R = 1 mA
6
8
10
V
I RM
V RM = 3V per line
500
nA
R I/O
900
1000
1100
Ω
R line
At 0V bias
80
100
120
pF
Figure 3: S21 (dB) attenuation measurement
and Aplac simulation
Figure 4: Analog crosstalk measurements
0.00
dB
0
- 5.00
Aplac
-20
- 10.00
Measure
- 15.00
- 20.00
-40
- 25.00
- 30.00
-60
- 35.00
-80
- 40.00
- 45.00
-100
- 50.00
1
10
100
1,000
1.0M
3.0M
10.0M
30.0M
100.0M
300.0M
1.0G
frequency (MHz)
f/Hz
2/7
I
0.00
dB
- 5.00
- 10.00
- 15.00
- 20.00
- 25.00
- 30.00
- 35.00
- 40.00
- 45.00
- 50.00
1.0M
3.0M
10.0M
30.0M
100.0M
300.0M
1.0G
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EMIF10-1K010F2
Figure5:Digitalcrosstalkmeasurement
Figure 6: ESD response to IEC61000-4-2
(+15kV air disc.harge) on one input V(in) and
on one output (Vout)
V G1
V(in1)
V(out1)
β
2 1 G1
Figure 7: ESD response to IEC61000-4-2 (-15kV
air discharge) on one input V(in) and on one
output (Vout)
Figure 8: Line capacitance versus applied
voltage
C(pF)
100
90
F=1MHz
Vosc=30mV
V(in1)
80
70
60
50
40
30
V(out1)
20
10
VR(V)
0
1
2
5
10
3/7
V
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EMIF10-1K010F2
Figure 9: Aplac model single line structure
Rs
Ls
50pH
50m
50pH
50m
Ls
Rs
GNDi
Ii
Oi
+
-
Port15
50
+
+
Port16
50
Lbump
cap_line
cap_line
Rbump
Rgnd
Lgnd
Rgnd
Lgnd
Rgnd
Lgnd
Rgnd
Lgnd
Rseries
Csubump
Rsubump
Lhole
Ii
Oi
+
Ii
+
cap_hole
MODEL = demif10
Rsub
sub
Rhole
GNDi
MODEL = demif10
Csubump
+
Rsubump
Oi
sub
Figure 10: Aplac model parameters
Cz
57pF
Model demif10
BV = 7
IBV = 1m
CJO = Cz
M = 0.3333
Rs = 1
VJ = 0.6
TT = 100n
Rseries
960
cap_line
0.8pF
Ls
0.6nH
Rbump
50m
Lbump
50pH
Rs
0.15
Csubump
15pF
Rsubump
0.15
Rsub
0.1
lhole
1.2nH opt
Rhole
0.15
cap_hole
0.15pF
Rgnd
0.25
Ignd
0.4nH
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EMIF10-1K010F2
Figure 11: Ordering Information Scheme
EMIF yy - xxx zz Fx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip-Chip
x = 1: 500µm, Bump = 315µm
= 2: Leadfree Pitch = 500µm, Bump = 315µm
= 3: Leadfree Pitch = 400µm, Bump = 250µm
Figure 12: FLIP-CHIP Package Mechanical Data
500µm ± 50
315µm ± 50
650µm ± 65
2.57mm ± 50µm
250µm ± 40
Figure 13: Foot print recommendations
Figure 14: Marking
5 4 5
400
Copper pad Diameter :
250µm recommended , 300µm max
Dot, ST logo
xx = marking
z = packaging
location
Solder stencil opening : 330µm
yww = datecode
(y = year
ww = week)
E
x
y
x
w
z
w
Solder mask opening recommendation :
340µm min for 315µm copper pad diameter
All dimensions in µm
5/7
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