VHDL-quick-start.pdf

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VHDL-quick-start
VHDL Quick Start
Peter J. Ashenden
The University of Adelaide
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Objective
• Quick introduction to VHDL
– basic language concepts
– basic design methodology
• Use The Student’s Guide to VHDL
or The Designer’s Guide to VHDL
– self-learning for more depth
– reference for project work
© 1998, Peter J. Ashenden
VHDL Quick Start
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Modeling Digital Systems
• VHDL is for writing models of a system
• Reasons for modeling
– requirements specification
– documentation
– testing using simulation
– formal verification
– synthesis
• Goal
– most reliable design process, with minimum cost and
time
– avoid design errors!
© 1998, Peter J. Ashenden
VHDL Quick Start
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Domains and Levels of Modeling
Structural
Functional
high level of
abstraction
low level of
abstraction
Geometric
“Y-chart” due to
Gajski & Kahn
© 1998, Peter J. Ashenden
VHDL Quick Start
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Domains and Levels of Modeling
Structural
Functional
Algorithm
(behavioral)
Register-Transfer
Language
Boolean Equation
Differential Equation
Geometric
“Y-chart” due to
Gajski & Kahn
© 1998, Peter J. Ashenden
VHDL Quick Start
5
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