Attiny 13 opis.pdf

Features

• High Performance, Low Power AVR ® 8-Bit Microcontroller

• Advanced RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

• Non-volatile Program and Data Memories

– 1K Byte of In-System Programmable Program Memory Flash

Endurance: 10,000 Write/Erase Cycles

– 64 Bytes In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– 64 Bytes Internal SRAM

– Programming Lock for Self-Programming Flash Program and EEPROM Data

Security

• Peripheral Features

– One 8-bit Timer/Counter with Prescaler and Two PWM Channels

– 4-channel, 10-bit ADC with Internal Voltage Reference

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low Power Idle, ADC Noise Reduction, and Power-down Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit

– Internal Calibrated Oscillator

• I/O and Packages

– 8-pin PDIP/SOIC: Six Programmable I/O Lines

• Operating Voltage:

– 1.8 - 5.5V for ATtiny13V

– 2.7 - 5.5V for ATtiny13

• Speed Grade

– ATtiny13V: 0 - 6 MHz @ 1.8 - 5.5V, 0 - 12 MHz @ 2.7 - 5.5V

– ATtiny13: 0 - 12 MHz @ 2.7 - 5.5V, 0 - 24 MHz @ 4.5 - 5.5V

• Industrial Temperature Range

• Low Power Consumption

– Active Mode:

1 MHz, 1.8V: 240µA

– Power-down Mode:

< 0.1µA at 1.8V

8-bit

Microcontroller

with 1K Bytes

In-System

Programmable

Flash

ATtiny13

Preliminary

Summary

Pin Configurations

Figure 1. Pinout ATtiny13

PDIP/SOIC

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

(PCINT4/ADC2) PB4

GND

VCC

PB2 (SCK/ADC1/T0/PCINT2)

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

Rev. 2535CS–AVR–02/04

Note: This is a summary document. A complete document

is available on our Web site at www.atmel.com.

2535CS–AVR–02/04

Overview

The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the

ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

Block Diagram

Figure 2. Block Diagram

8-BIT DATABUS

STACK

POINTER

CALIBRATED

WATCHDOG

OSCILLATOR

INTERNAL

OSCILLATOR

SRAM

WATCHDOG

TIMER

TIMING AND

CONTROL

VCC

PROGRAM

COUNTER

MCU CONTROL

GND

MCU STATUS

PROGRAM

FLASH

TIMER/

COUNTER0

INSTRUCTION

GENERAL

PURPOSE

REGISTERS

INTERRUPT

UNIT

PROGRAMMING

LOGIC

INSTRUCTION

DECODER

CONTROL

LINES

ALU

DATA

EEPROM

STATUS

ADC /

ANALOG COMPARATOR

DATA REGISTER

PORT B

DATA DIR.

REG.PORT B

PORT B DRIVERS

RESET

CLKI

PB0-PB5

ATtiny13

2535CS–AVR–02/04

ATtiny13

The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

The ATtiny13 provides the following features: 1K byte of In-System Programmable

Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general pur-

pose working registers, one 8-bit Timer/Counter with compare modes, Internal and

External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with

internal Oscillator, and three software selectable power saving modes. The Idle mode

stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and

Interrupt system to continue functioning. The Power-down mode saves the register con-

tents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC

Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize

switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology.

The On-chip ISP Flash allows the Program memory to be re-programmed In-System

through an SPI serial interface, by a conventional non-volatile memory programmer or

by an On-chip boot code running on the AVR core.

The ATtiny13 AVR is supported with a full suite of program and system development

tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir-

cuit Emulators, and Evaluation kits.

Pin Descriptions

VCC

Digital supply voltage.

GND

Ground.

Port B (PB5..PB0)

Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny13 as listed on

page 49.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a reset, even if the clock is not running. The minimum pulse length is given in Table

12 on page 30. Shorter pulses are not guaranteed to generate a reset.

2535CS–AVR–02/04

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x3F

SREG

page 6

0x3E

Reserved

–

0x3D

SPL

SP[7:0]

page 8

0x3C

Reserved

–

0x3B

GIMSK

–

INT0

PCIE

–

page 53

0x3A

GIFR

–

INTF0

PCIF

–

page 53

0x39

TIMSK0

–

OCIE0B

OCIE0A

TOIE0

–

page 70

0x38

TIFR0

–

OCF0B

OCF0A

TOV0

–

page 71

0x37

SPMCSR

–

CTPB

RFLB

PGWRT

PGERS

SELFPRGEN

page 97

0x36

OCR0A

Timer/Counter – Output Compare Register A

page 70

0x35

MCUCR

–

PUD

SM1

SM0

–

ISC01

ISC00

page 49

0x34

MCUSR

–

WDRF

BORF

EXTRF

PORF

page 33

0x33

TCCR0B

FOC0A

FOC0B

–

WGM02

CS02

CS01

CS00

page 66

0x32

TCNT0

Timer/Counter (8-bit)

page 70

0x31

OSCCAL

Oscillator Calibration Register

page 22

0x30

Reserved

–

0x2F

TCCR0A

COM0A1

COM0A0

COM0B1

COM0B0

–

WGM01

WGM00

page 69

0x2E

DWDR

DWDR[7:0]

page 94

0x2D

Reserved

–

0x2C

Reserved

–

0x2B

Reserved

–

0x2A

Reserved

–

0x29

OCR0B

Timer/Counter – Output Compare Register B

page 70

0x28

GTCCR

TSM

–

PSR10

page 73

0x27

Reserved

–

0x26

CLKPR

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

page 24

0x25

Reserved

–

0x24

Reserved

–

0x23

Reserved

–

0x22

Reserved

–

0x21

WDTCR

WDTIF

WDTIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

page 37

0x20

Reserved

–

0x1F

Reserved

–

0x1E

EEARL

–

EEPROM Address Register

page 14

0x1D

EEDR

EEPROM Data Register

page 14

0x1C

EECR

–

EEPM1

EEPM0

EERIE

EEMWE

EEWE

EERE

page 15

0x1B

Reserved

–

0x1A

Reserved

–

0x19

Reserved

–

0x18

PORTB

–

PORTB5

PORTB4

PORTB3

PORTB2

PORTB1

PORTB0

page 51

0x17

DDRB

–

DDB5

DDB4

DDB3

DDB2

DDB1

DDB0

page 51

0x16

PINB

–

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

page 51

0x15

PCMSK

–

PCINT5

PCINT4

PCINT3

PCINT2

PCINT1

PCINT0

page 54

0x14

DIDR0

–

ADC0D

ADC2D

ADC3D

ADC1D

EIN1D

AIN0D

page 76, page 91

0x13

Reserved

–

0x12

Reserved

–

0x11

Reserved

–

0x10

Reserved

–

0x0F

Reserved

–

0x0E

Reserved

–

0x0D

Reserved

–

0x0C

Reserved

–

0x0B

Reserved

–

0x0A

Reserved

–

0x09

Reserved

–

0x08

ACSR

ACD

ACBG

ACO

ACI

ACIE

–

ACIS1

ACIS0

page 74

0x07

ADMUX

–

REFS0

ADLAR

–

MUX1

MUX0

page 88

0x06

ADCSRA

ADEN

ADSC

ADATE

ADIF

ADIE

ADPS2

ADPS1

ADPS0

page 89

0x05

ADCH

ADC Data Register High Byte

page 90

0x04

ADCL

ADC Data Register Low Byte

page 90

0x03

ADCSRB

–

ACME

–

ADTS2

ADTS1

ADTS0

page 91

0x02

Reserved

–

0x01

Reserved

–

0x00

Reserved

–

ATtiny13

2535CS–AVR–02/04

ATtiny13

Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

2535CS–AVR–02/04

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