LM1881.PDF

February 1995

LM1881 Video Sync Separator

General Description

The LM1881 Video sync separator extracts timing informa-

tion including composite and vertical sync, burst/back porch

timing, and odd/even field information from standard nega-

tive going sync NTSC, PAL*, and SECAM video signals with

amplitude from 0.5V to 2V p-p. The integrated circuit is also

capable of providing sync separation for non-standard, fast-

er horizontal rate video signals. The vertical output is pro-

duced on the rising edge of the first serration in the vertical

sync period. A default vertical output is produced after a

time delay if the rising edge mentioned above does not oc-

cur within the externally set delay period, such as might be

the case for a non-standard video signal.

Features

Y AC coupled composite input signal

Y l 10 k X input resistance

Y k 10 mA power supply drain current

Y Composite sync and vertical outputs

Y Odd/even field output

Y Burst gate/back porch output

Y Horizontal scan rates to 150 kHz

Y Edge triggered vertical output

Y Default triggered vertical output for non-standard video

signal (video games-home computers)

Connection Diagram

LM1881N

TL/H/9150±1

Order Number LM1881M or LM1881N

See NS Package Number M08A or N08E

*PAL in this datasheet refers to European broadcast TV standard ``Phase Alternating Line'', and not to Programmable Array Logic.

C 1995 National Semiconductor Corporation

TL/H/9150

RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage

Storage Temperature Range

b 65 § Cto a 150 § C

ESD Susceptibility (Note 2)

2 kV

13.2V

Soldering Information

Dual-In-Line Package (10 sec.)

260 § C

Input Voltage

3 Vpp (V CC e 5V)

6 Vpp (V CC t 8V)

Small Outline Package

Vapor Phase (60 sec.) 215 § C

Infrared (15 sec.) 220 § C

See AN-450 ``Surface Mounting Methods and their Effect on

Product Reliability'' for other methods of soldering surface

mount devices.

Output Sink Currents; Pins 1, 3, 5

5 mA

Output Sink Current; Pin 7

2 mA

Package Dissipation (Note 1)

1100 mW

Operating Temperature Range

0 § C b 70 § C

Electrical Characteristics

V CC e 5V; Rset e 680 k X ;T A e 25 § C; Unless otherwise specified

Parameter

Conditions

Typ

Tested

Design

Units

Limit (Note 3) Limit (Note 4)

(Limits)

Supply Current

Outputs at Logic 1 V CC e 5V 5.2

mAmax

V CC e 12V 5.5

mAmax

DC Input Voltage

Pin 2

1.5

1.3

Vmin

1.8

Vmax

Input Threshold Voltage

Note 5

mVmin

mVmax

Input Discharge Current

Pin 2; V IN e 2V

m Amin

m Amax

Input Clamp Charge Current Pin 2; V IN e 1V

0.8

0.2

mAmin

R SET Pin Reference Voltage Pin 6; Note 6

1.22

1.10

Vmin

1.35

Vmax

Composite Sync. & Vertical

I OUT e 40 m A;

V CC e 5V 4.5

4.0

Vmin

Outputs

Logic 1

V CC e 12V

11.0

Vmin

I OUT e 1.6 mA

V CC e 5V 3.6

2.4

Vmin

Logic 1

V CC e 12V

10.0

Vmin

Burst Gate & Odd/Even

I OUT e 40 m A;

V CC e 5V 4.5

4.0

Vmin

Outputs

Logic 1

V CC e 12V

11.0

Vmin

Composite Sync. Output

I OUT eb 1.6 mA; Logic 0; Pin 1

0.2

0.8

Vmax

Vertical Sync. Output

I OUT eb 1.6 mA; Logic 0; Pin 3

0.2

0.8

Vmax

Burst Gate Output

I OUT eb 1.6 mA; Logic 0; Pin 5

0.2

0.8

Vmax

Odd/Even Output

I OUT eb 1.6 mA; Logic 0; Pin 7

0.2

0.8

Vmax

Vertical Sync Width

230

190

m smin

300

m smax

Burst Gate Width

2.7 k X from Pin 5 to V CC

2.5

m smin

4.7

m smax

65 32 m smin

90 m smax

Note 1: For operation in ambient temperatures above 25 § C, the device must be derated based on a 150 § C maximum junction temperature and a package thermal

resistance of 110 § C/W, junction to ambient.

Note 2: ESD susceptibility test uses the ``human body model, 100 pF discharged through a 1.5 k X resistor''.

Note 3: Typicals are at T J e 25 § C and represent the most likely parametric norm.

Note 4: Tested Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 5: Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse.

Note 6: Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins 1, 3, 5, and 7) to the R SET pin (Pin 6).

Note 7: Delay time between the start of vertical sync (at input) and the vertical output pulse.

Note 7

Vertical Default Time

Typical Performance Characteristics

R set Value Selection

Vertical Default

vs Vertical Serration

Sync Delay Time

Burst/Black Level

Pulse Separation

vs Rset

Gate Time vs Rset

Vertical Pulse

Supply Current vs

Width vs Rset

Width vs Temperature

Supply Voltage

TL/H/9150±2

Application Notes

The LM1881 is designed to strip the synchronization signals

from composite video sources that are in, or similar to, the

N.T.S.C. format. Input signals with positive polarity video (in-

creasing signal voltage signifies increasing scene bright-

ness) from 0.5V (p-p) to 2V (p-p) can be accommodated.

The LM1881 operates from a single supply voltage between

5V DC and 12V DC. The only required external components

beside power supply and set current decoupling are the in-

put coupling capacitor and a single resistor that sets internal

current levels, allowing the LM1881 to be adjusted for

source signals with line scan frequencies differing from

15.734 kHz. Four major sync signals are available from the

I/C: composite sync including both horizontal and vertical

scan timing information; a vertical sync pulse; a burst gate

or back porch clamp pulse; and an odd/even output. The

odd/even output level identifies which video field of an inter-

laced video source is present at the input. The outputs from

the LM1881 can be used to gen-lock video camera/VTR

signals with graphics sources, provide identification of video

fields for memory storage, recover suppressed or contami-

nated sync signals, and provide timing references for the

extraction of coded or uncoded data on specific video scan

lines.

To better understand the LM1881 timing information and

the type of signals that are used, refer to Figure 2(a±e)

which shows a portion of the composite video signal from

the end of one field through the beginning of the next field.

COMPOSITE SYNC OUTPUT

The composite sync output, Figure2(b), is simply a repro-

duction of the signal waveform below the composite video

black level, with the video completely removed. This is ob-

tained by clamping the video signal sync tips to 1.5V DC at

Pin 2 and using a comparator threshold set just above this

voltage to strip the sync signal, which is then buffered out to

Pin 1. The threshold separation from the clamped sync tip is

nominally 70 mV which means that for the minimum input

level of 0.5V (p-p), the clipping level is close to the halfway

point on the sync pulse amplitude (shown by the dashed

line on Figure2(a) ). This threshold separation is indepen-

dent of the signal amplitude, therefore, for a 2V (p-p) input

the clipping level occurs at 11% of the sync pulse ampli-

tude. The charging current for the input coupling capacitor is

0.8 mA, whereas the discharge current is only 11 m A, typi-

cally. This allows relatively small capacitor values to be

usedÐ0.1 m F is generally recommended.

Normally the signal source for the LM1881 is assumed to be

clean and relatively noise-free, but some sources may have

excessive video peaking, causing high frequency video and

chroma components to extend below the black level refer-

ence. Some video discs keep the chroma burst pulse pres-

ent throughout the vertical blanking period so that the burst

actually appears on the sync tips for three line periods in-

stead of at black level. A clean composite sync signal can

be generated from these sources by filtering the input sig-

nal. When the source impedance is low, typically 75 X ,a

620 X resistor in series with the source and a 510 pF capaci-

tor to ground will form a low pass filter with a corner fre-

quency of 500 kHz. This bandwidth is more than sufficient to

pass the sync pulse portion of the waveform; however, any

subcarrier content in the signal will be attenuated by almost

18 dB, effectively taking it below the comparator threshold.

Filtering will also help if the source is contaminated with

thermal noise. The output waveforms will become delayed

from between 40 ns to as much as 200 ns due to this filter.

This much delay will not usually be significant but it does

contribute to the sync delay produced by any additional sig-

nal processing. Since the original video may also undergo

processing, the need for time delay correction will depend

on the total system, not just the sync stripper.

VERTICAL SYNC OUTPUT

A vertical sync output is derived by internally integrating the

composite sync waveform (Figure 3). To understand the

generation of the vertical sync pulse, refer to the lower left

hand section Figure3. Note that there are two comparators

in the section. One comparator has an internally generated

voltage reference called V 1 going to one of its inputs. The

other comparator has an internally generated voltage refer-

ance called V 2 going to one of its inputs. Both comparators

have a common input at their noninverting input coming

from the internal integrator. The internal integrator is used

for integrating the composite sync signal. This signal comes

from the input side of the composite sync buffer and are

positive going sync pulses. The capacitor to the integrator

is internal to the LM1881. The capacitor charge current is

set by the value of the external resistor R set . The output of

the integrator is going to be at a low voltage during the

normal horizontal lines because the integrator has a very

short time to charge the capacitor, which is during the hori-

zontal sync period. The equalization pulses will keep the

output voltage of the integrator at about the same level,

below the V 1 . During the vertical sync period the narrow

going positive pulses shown in Figure2 is called the serra-

tion pulse. The wide negative portion of the vertical sync

period is called the vertical sync pulse. At the start of the

vertical sync period, before the first Serration pulse occurs,

the integrator now charges the capacitor to a much higher

voltage. At the first serration pulse the integrator output

should be between V 1 and V 2 . This would give a high level

at the output of the comparator with V 1 as one of its inputs.

This high is clocked into the ``D'' flip-flop by the falling edge

of the serration pulse (remember the sync signal is inverted

in this section of the LM1881). The ``Q'' output of the ``D''

flip-flop goes through the OR gate, and sets the R/S flip-

flop. The output of the R/S flip-flop enables the internal

oscillator and also clocks the ODD/EVEN ``D'' flip-flop. The

ODD/EVEN field pulse operation is covered in the next sec-

tion. The output of the oscillator goes to a divide by 8 circuit,

thus resetting the R/S flip-flop after 8 cycles of the oscilla-

tor. The frequency of the oscillator is established by the

internal ca pa citor going to the oscillator and the external

R set . The ``Q'' output of the R/S flip-flop goes to pin 3 and is

the actual vertical sync output of the LM1881. By clocking

the ``D'' flip-flop at the start of the first serration pulse

means that the vertical sync output pulse starts at this point

in time and lasts for eight cycles of the internal oscillator as

shown in Figure2.

How R set affects the integrator and the internal oscillator is

shown under the Typical Performance Characteristics. The

first graph is ``R set Value Selection vs Vertical Serration

Pulse Separation''. For this graph to be valid, the vertical

sync pulse should last for at least 85% of the horizontal half

line (47% of a full horizontal line). A vertical sync pulse from

any standard should meet this requirement; both NTSC and

PAL do meet this requirement (the serration pulse is the

remainder of the period, 10% to 15% of the horizontal

Application Notes (Continued)

TL/H/9150±3

FIGURE 2. (a) Composite Video; (b) Composite Sync; (c) Vertical Output Pulse;

(d) Odd/Even Field Index; (e) Burst Gate/Back Porch Clamp

*Components Optional,

TL/H/9150±4

See Text

FIGURE 3

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika: