LH0024_LH0032.pdf

LH0024 and LH0032 High

Speed Op Amp

Applications

National Semiconductor

Application Note 253

January 1982

INTRODUCTION

The LH0024 and LH0032 are very high speed general pur-

pose operational amplifiers exhibiting 70 MHz bandwidths,

500 V/ m s slew rates and 100 to 300 ns settling time to

0.1%. The LH0032 has the added advantage of FET input

characteristics. Both, however, can drive loads with peak

currents of 100 milliamperes (mA). The op amps are stable

without external compensation when operating at closed-

loop gains of more than 100. Both are constructed with thick

film hybrid technology and are actively trimmed for consist-

ent device performance. Table I summarizes the typical per-

formance data for these op amps. Additional information

may be obtained from the respective data sheets.

This note is divided into three parts, with the first giving a

general description of the circuit topology of each op amp.

In the following section, several high performance applica-

tions are discussed. Finally, the last section consolidates all

application techniques into an integral design approach,

much of which is applicable to any high frequency circuit.

LH0024 CIRCUIT DESCRIPTION

The LH0024 contains two gain stages: One is a differential

NPN pair and the other is a single-ended PNP stage. The

complete schematic is shown in Figure1.

The input stage differential pair, Q8 and Q9, is biased at

6 mA by a current source made up of Q1, Q2, R3, and R5.

First stage differential voltage gain is typically 2. Its output is

applied differentially from base to emitter of the second

stage transistor Q3 which has a gain of about 1,700. This

stage also converts the differential signal to a single-ended

output.

Current source Q5 and R4 provide 5 mA of DC bias current

and a high impedance load to Q3. Overall amplifier gain is

the product of the gains of the two stagesÐ2 x 1700 e

3,400, or 71 dB.

The output complementary pair with class B bias provides a

low impedance sourcing and sinking output drive. Although

the class B bias contributes a small amount of cross-over

distortion, it is barely detectable in closed loop operation.

LH0032 CIRCUIT DESCRIPTION

The LH0032 is a general purpose operational amplifier simi-

lar to the LH0024, but with JFET input devices instead of

bipolar. As a result, the LH0032 DC input bias and offset

currents are three orders of magnitude lower than the

LH0024. Its output drive capability is improved due to the

use of a larger package with lower thermal resistance, and

its class AB output, which is normally biased on, virtually

eliminates cross-over distortion.

The improved DC performance is due, in part, to the incor-

poration of monolithic dual junction FETs in the input stage

of the LH0032, providing matched DC tracking and good

TL/H/7313±1

FIGURE 1. Complete LH0024 Schematic Diagram

TABLE I. TypicalPerformance Characteristics

Parameter (T A e 25 § C)

Conditions

LH0024

LH0032

Units

Input Offset Voltage

Input Bias Current

15 m A

10 pA

Large Signal Voltage Gain

V OUT e g 10V

f e 1 kHz, R L e 1k X

Slew Rate

A V ea 1, D V IN e 20V

500

V/ m s

Small Signal Rise Time

A V ea 1, D V IN e 1V

Settling Time to 1.0% of Final Value

A V eb 1, D V IN e 20V

100

Settling Time to 0.1% of Final Value

275

300

Unity Gain Bandwidth

(uncompensated)

Mhz

C 1995 National Semiconductor Corporation

TL/H/7313

RRD-B30M115/Printed in U. S. A.

common-mode input characteristics. First stage operating

current is set at 6 mA by the current source made up of

transistors Q8 and Q9 and resistors R4 and R9, as shown in

Figure2. The first stage voltage gain is:

A V (1st stage) e g m R L e 1.4

Where: g m4 e

5mA

0.026V

h oe10 ll ( b 11 a 1) (R L )

Notice that the full differential gain is realized with the use of

the current mirror Q10 and Q16, which also provides high

active load resistance to the PNP cascoded pair, resulting in

high amplifier gain.

The collector output of the cascode stage is buffered by a

pair of complementary emitter follower transistors, Q11 and

Q12. This class AB output stage is normally biased at 1 mA

by the 1.8 V BE voltage produced by Q7, R5, and R6. The

emitter degeneration resistors provide protection from ther-

mal runaway.

APPLICATIONS OF THE LH0024/LH0032

Applications of the high speed LH0024 and LH0032 range

from video amplifiers to sampling circuits. The applications

described below include high speed sample and hold cir-

cuits, photo-detector amplifiers, fast settling digital to analog

converters and buffered amplifiers.

h ob6 ll 1

(1)

Where: gm e 3.5 mmho

R L e R 1 ll ( b 3 a 1) (r e3 a 2R 3 )

The second stage consists of two identical pairs of differen-

tial PNP transistors in a cascode configuration. Each side

operates at 5 mA set by the emitter resistor R3 and the bias

of the first stage. The differential amplifier Q3 and Q4 feeds

the common-base pair Q5 and Q6 with the base voltage

fixed at V a b 1.9 volts by the diode string Q13±A15. Thus

the collectors of the differential pair Q3 and Q4 are held at

one V BE drop more positive than the reference voltage. Any

signal amplified by the differential stage produces only a

very small change in Q3 nd Q4 collector voltage. Conse-

quently, the Miller effect on Q3 and Q4 (base-to-collector

capacitances) is virtually eliminated. Using hybrid q model

of the transistor, the voltage gain of the cascode stage may

be approximated as:

A V (2nd stage) e g m4 xR eq j 1,400

(2)

TL/H/7313±2

FIGURE 2. Complete LH0032 Schematic Diagram

TL/H/7313±3

FIGURE 3. High Speed Sample and Hold Circuit

R eq e

A High Speed S/H Circuit

High Speed sample-and-hold circuits require high slew rate

and fast settling amplifiers. The LH0032 is ideal for these

applications. An example is shown in Figure3.

The complementary emitter-follower Q3 and Q4 sources or

sinks large peak current to rapidly charge or discharge the

hold capacitor during step changes, thus effectively buffer-

ing the FET switch, Q1, whose r D(ON) would otherwise slow

the charge time. The LH0033 FET-input amplifier buffers the

output signal, providing 100 mA drive capability.

The circuit exhibits a 10V acquisition time of 900 ns to 0.1%

accuracy and a droop rate of only 100 m V/ms at 25 § C ambi-

ent condition. An even faster acquisition time can be ob-

tained using a smaller value hold-capacitor. By decreasing

the value from 1000 pF to 220 pF, the acquisition time im-

proves to 500 ns for a 10V step. However, droop rate in-

creases to 500 m V/ms.

Fiber Optic Transmitter-Receiver Applications

Many fiber optic applications require analog drivers and re-

ceivers operating in the megahertz region where many so-

called wide-band op amps simply run out of steam. Packed

with 70 MHz gain-bandwidth product (unity gain compensat-

ed), the LH0032 is quite suitable for optical communication

applications up to 3.5 MHz. Figure4 demonstrates a com-

plete analog transmission system using this device.

The transmitter incorporates the LF356 to drive the light

emitter. The LED is normally biased at 50 mA operating

current. The input is capacitively coupled and ranges from

0V to 5V, modulating the LED current from 0 mA to

100 mA. The circuit can be easily modified to operate from a

single a 15V power supply. The only requirement is that the

amplifier must be biased within the input common mode

range.

The receiver circuit uses an LH0032 configured as a trans-

impedance amplifier. A photodiode with 0.5 amp per watt

responsivity such as the Hewlett-Packard type HP5082-

4220, generates 50 mV signal at the receiver output for

1 m W of light input.

Expectedly, the bandwidth of the entire optical link rests on

the receiver circuit. Therefore, if the response time is to be

optimized, one should reverse bias the photodiode to mini-

mize junction capacitance. As a result, rise time improves

more than 2 orders of magnitude. Next, the feedback resis-

tor value should be chosen to be as large as possible in

order to maximize sensitivity within the limits of allowable

bandwidth degradation. Using 100 k X feedback resistor, the

maximum system bandwidth is 3.5 MHz.

Fast Settling 12-BIT D/A Converter

A high resolution, fast-settling DAC can be constructed us-

ing the LH0032. Its low input bias current causes no signifi-

cant DC error in conversion accuracy. Great care must be

exercised in circuit layout to assure highest performance. A

single point analog ground should be used with the digital

ground separated. A complete circuit with 12-bit resolution

is shown in Figure 5. The converter typically settles to

(/2

TL/H/7313±4

FIGURE 4. Fiber Optic Link

TL/H/7313±5

FIGURE 5. Fast Settling DAC

LSB in 800 ns for a 10V full-scale swing. Similarly, 10-bit

or 8-bit resolution DACs may be constructed using the

DAC1020 or DAC0808, respectively.

Buffered Amplifier

Whenever higher output current is required, a buffer amplifi-

er may be added to the loop as shown in Figure 6. The

LH0033 boosts the output drive capability to g 100 mA con-

tinuous and g 400 mA peak.

DESIGN CONSIDERATIONS

Optimizing LH0024/32 Performance

The LH0024 and LH0032 allow considerable flexibility in de-

signing high performance circuits if care is taken in the way

they are used and implemented. Indeed, the printed circuit

board layout in high frequency circuits is as important as the

design of the hybrid devices themselves.

It is good practice to use ground plane PC board design. It

provides a low resistance, low inductance path, and reduc-

es stray signal coupling to sensitive circuitry. A double-sided

ground plane is usually better and should be considered.

In addition, signal trace connections should be kept as short

and wide as possible. Avoid closely-spaced parallel signal

traces as signal cross-coupling may occur. Circuit elements

should be placed close to the amplifier, particularly critical

components that directly affect the amplifier's frequency re-

sponse, such as compensation capacitors. If at all possible,

one should maintain single point ground throughout the cir-

cuit to minimize signal phase delay.

Examples of single-sided PC layouts for the LH0024 and

LH0032 are shown in Figure7 and Figure8, respectively.

The layouts include a settling time test circuit, optional in-

verting or noninverting mode. Note that the summing junc-

tion side of the feedback resistor is kept very close to the

device pin, thus minimizing lead capacitance. The power

supply decoupling capacitors should also be kept close to

the device pins, preferably

TL/H/7313±6

FIGURE 6. Wide Band Amplifier

with 100 mA Output Capability

Despite its 100 MHz bandwidth, the LH0033 introduces

about 15 degrees of phase lag at the LH0032 unity-gain

frequency of 70 MHz. As a result, phase margin is degraded

by the same amount. Slight overcompensation may be re-

quired in order to restore adequate phase margin. One way

is to increase the feedback capacitor from 5 pF to a slightly

larger value, 6 to 8 pF should be sufficient. If the load is

predominantly capacitive, the total phase shift of the buffer

stage may exceed 180 § and appear as negative impedance

seen looking into the input of the buffer. The 51 X resistor

restores some real resistance to alleviate this condition and

prevents potential oscillation. In cases where the load ca-

pacitance is relatively large, up to 100 X may be necessary

to compensate for it.

of an inch.

Input Guarding and Bootstrapping

In applications where input leakage currents are important,

trace guarding, such as used in sample and hold circuits,

can improve performance at no additional cost.

*/8

TL/H/7313±7

TL/H/7313±8

FIGURE 7. Single-Sided Sample PC Layout for LH0024

TL/H/7313±9

TL/H/7313±12

FIGURE 8. Single-Sided Sample PC Layout for LH0032

The guard conductor serves to intercept leakage currents

from inputs to the surrounding circuit. It is most effective

when it is driven to the same potential as the guarded cir-

cuit. Figures 9 and 10 show how the technique is imple-

mented in inverting and non-inverting configurations, re-

spectively.

One other benefit of input guarding is the reduction of input

stray capacitance effects. A comprehensive discussion of

this technique is described in Application Note AN-63.

Input Capacitance Cancellation

The intrinsic input capacitance of the amplifier cannot be

totally eliminated by the input guarding technique. This input

capacitance introduces a pole in the amplifier response at

the frequency given by:

f p e

2 q R S C IN

(3)

This pole may become extremely important as, for example,

aC IN of 5 pF (typical input capacitance of the LH0024 and

LH0032) with a 500 X effective source resistance creates a

pole at about 64 MHzÐwell before the amplifier's natural

frequency response rolls off to unity gain at 70 MHz. If

closed-loop gain is unity, more than 135 § total phase lag is

introduced even before the crossover frequency is reached

and will destroy phase margin. Oscillation is certain to oc-

cur. The solution is to cancel its effect. As shown in Figure

11, the lead capacitor C1 across the feedback resistor is

used to introduce a zero in the loop response such that it

exactly cancels the pole caused by the input RC network.

TL/H/7313±10

FIGURE 9. Guarding Inverting Figure Amplifier

TL/H/7313±13

FIGURE 11. Compensating Amplifier Input Capacitance

TL/H/7313±11

FIGURE 10. Guarding Non-Inverting

Unity Gain Amplifier

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