54ACT112.pdf
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Pobierz
September 1998
54ACT112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The ’ACT112 contains two independent, high-speed JK
flip-flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trigger-
ing occurs at a voltage level of the clock and is not directly
related to the transition time. The J and K inputs can change
when the clock is in either state without affecting the flip-flop,
provided that they are in the desired state during the recom-
mended setup and hold tim
es
rela
tiv
e to the falling edge of
the clock. A
LO
W signal on S
D
or C
D
prevents clocking and
forces Q or Q
HIG
H, respectively. Si
m
ultaneous LOW sig-
nals on S
D
and C
D
force both Q and Q HIGH.
Asynchronous In
p
uts:
LOW input to
S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are inde
pe
ndent
o
f clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
n
’ACT112 has TTL-compatible inputs
n
Outputs source/sink 24 mA
n
Standard Microcircuit Drawing (SMD) 5962-8995001
Connection Diagram
Pin Descriptions
Pin Names
Description
Pin Assigment for
DIP and Flatpack
J
1
,
J
2
,K
1
,K
2
Data Inputs
CP
1
,CP
2
Clock Pulse Inputs
(Active Falling Edge)
C
D1
,
C
D2
Direct Clear Inputs (Active LOW)
S
D1
,S
D2
Direct Set Inputs (Active LOW)
Q
1
,Q
2
,Q
1
,Q
2
Outputs
DS100976-3
Pin Assigment
for LCC
DS100976-5
FACT
™
is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100976
www.national.com
Logic Symbols
DS100976-2
DS100976-1
IEEE/IEC
DS100976-4
Truth Table
Inp
uts
Output
s
S
D
C
D
CP
J
K Q Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H
H
H
H
Mh
h
Q
0
Q
0
H
H
Ml
h
L
H
H
H
Mh
l
H
L
H
H
Ml
l
Q
0
Q
0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
M =
H
IGH-to-LOW Clock Transition
Q
0
(Q
0
) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock
transition.
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2
Logic Diagram
(One Half Shown)
DS100976-6
3
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
Junction Temperature (T
J
)
CDIP
175˚C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
−0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=
−0.5V
4.5V to 5.5V
−20 mA
Input Voltage (V
I
)
0VtoV
CC
V
I
=
V
CC
+ 0.5V
+20 mA
Output Voltage (V
O
)
0VtoV
CC
DC Input Voltage (V
I
)
−0.5V to V
CC
+ 0.5V
Operating Temperature (T
A
)
−55˚C to +125˚C
DC Output Diode Current (I
OK
)
V
O
=
−0.5V
Minimum Input Edge Rate (
D
V/
D
t)
125 mV/ns
−20 mA
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. Fairchild does not recom-
mend operation of FACT
™
circuits outside databook specifications.
V
O
=
V
CC
+ O.5
+20 mA
DC Output Voltage (V
O
)
−0.5V to V
CC
+0.5V
DC Output Source
or Sink Current (I
O
)
±
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
±
50 mA
Storage Temperature (T
STG
)
−65˚C to +150˚C
DC Characteristics for ’ACT Family Devices
Symbol
T
A
=
−55˚C to +125˚C
Parameter
V
CC
Units
Conditions
(V)
Guaranteed Limits
V
IH
Minimum High Level
4.5
2.0
V
V
OUT
= 0.1V
Input Voltage
5.5
2.0
or V
CC
− 0.1V
V
IL
Maximum Low Level
4.5
0.8
V
V
OUT
= 0.1V
Input Voltage
5.5
0.8
or V
CC
− 0.1V
V
OH
Minimum High Level
4.5
4.4
V
I
OUT
= −50 µA
Output Voltage
5.5
5.4
V
IN
= V
IL
or V
IH
4.5
3.70
V
I
OH
= −24 mA
5.5
4.70
I
OH
= −24 mA
(Note 2)
I
OUT
=
50 µA
V
OL
Maximum Low Level
4.5
0.1
V
Output Voltage
5.5
0.1
V
IN
=
V
IL
or V
IH
I
OL
=
24 MA
4.5
0.5
V
I
OL
=
24 mA
(Note 2)
5.5
0.5
V
I
=
V
CC
, GND
I
IN
Maximum Input Leakage
Current
±
1.0
5.5
µA
V
I
=
V
CC
− 2.1V
I
CCT
Maximum I
CC
/Input
5.5
1.6
mA
V
OLD
=
1.65V Max
I
OLD
Minimum Dynamic
5.5
50
mA
V
OHD
=
3.85V Min
I
OHD
Output Current(Note 3)
5.5
−50
mA
V
IN
=
V
CC
or GND
I
CC
Maximum Quiescent
Supply Current
5.5
80.0
µA
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
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4
AC Electrical Characteristics for ’ACT Family Devices
Symbol
T
A
=
−55˚C to +125˚C
Parameter
V
CC
Units
C
L
=
50 pF
(V)
(Note
4)
Min
Max
f
max
Maximum Clock
5.0
80
MHz
Frequency
t
PLH
Propagation
De
lay
5.0
1.0
14.0
ns
CP
n
to Q
n
or Q
n
t
PHL
Propagation
De
lay
5.0
1.0
14.0
ns
CP
n
to Q
n
or Q
n
t
PLH
P
ropag
a
tion Delay
5.0
1.0
13.5
ns
C
Dn
or S
Dn
to Q
n
or Q
n
t
PHL
P
ropag
a
tion Delay
5.0
1.0
13.5
ns
C
Dn
or S
Dn
to Q
n
or Q
n
Note 4:
Voltage Range 5.0 is 5.0V
±
0.5V
AC Operating Requirements:
Symbol
Parameter
V
CC
T
A
= −55˚C to +125˚C
Units
(V)
C
L
= 50 pF
(Note 5)
Guaranteed Minimum
t
S
Setup Time, HIGH or
LOW
5.0
8.0
ns
J
n
or K
n
to CP
n
t
H
Hold Time, HIGH or
LOW
5.0
1.5
ns
J
n
or K
n
to CP
n
t
W
Pulse W
id
th
5.0
5.0
ns
CP
n
or C
Dn
or S
Dn
t
rec
R
ecove
r
y Time
5.0
3.0
ns
C
Dn
or S
Dn
to CP
n
Note 5:
Voltage Range 5.0 is 5.0V
±
0.5V
Capacitance
Symbol
Parameter
Max
Units
Conditions
V
CC
=
OPEN
C
IN
Input Capacitance
10.0
pF
V
CC
=
5.0V
C
PD
Power Dissipation Capacitance
60
pF
5
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