54AC299.pdf

September 1998

54AC299 • 54ACT299

8-Input Universal Shift/Storage Register with Common

Parallel I/O Pins

General Description

The ’AC/’ACT299 is an 8-bit universal shift/storage register

with TRI-STATE ® outputs. Four modes of operation are pos-

sible: hold (store), shift left, shift right and load data. The par-

allel load inputs and flip-flop outputs are multiplexed to re-

duce the total number of package pins. Additional outputs

are provided for flip-flops Q 0 ,Q 7 to allow easy serial cascad-

ing. A separate active LOW Master Reset is used to reset the

n Common parallel I/O for reduced pin count

n Additional serial inputs and outputs for expansion

n Four operating modes: shift left, shift right, load and

store

n TRI-STATE outputs for bus-oriented applications

n Outputs source/sink 24 mA

n ’ACT299 has TTL-compatible inputs

n Standard Microcircuit Drawing (SMD)

’AC299: 5962-88754

’ACT299: 5962-88771

Features

n I CC and I OZ reduced by 50%

Ordering Code:

Logic Symbols

Connection Diagrams

Pin Assignment

for DIP and Flatpak

DS100252-1

IEEE/IEC

DS100252-2

Pin Assignment for LCC

DS100252-3

DS100252-4

TRI-STATE ® is a registered trademark of National Semiconductor Corporation.

FACT ® is a registered trademark of Fairchild Semiconductor Corporation.

DS100252

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Connection Diagrams (Continued)

Pin Names

Description

Clock Pulse Input

DS 0

Serial Data Input for Right Shift

DS 7

Serial Data Input for Left Shift

S 0 , S 1

Mode Select Inputs

Asynchronous Master Reset

OE 1 ,OE 2

TRI-STATE Output Enable Inputs

I/O 0 –I/O 7

Parallel Data Inputs or

TRI-STATE Parallel Outputs

Q 0 ,Q 7

Serial Outputs

Functional Description

The ’AC/’ACT299 contains eight edge-triggered D-type

flip-flops and the interstage logic necessary to perform syn-

chronous shift left, shift right, parallel load and hold opera-

tions. The type of operation is determined by S 0 and S 1 ,as

shown in the Truth Table. All flip-flop outputs are brought out

through TRI-STATE buffers to separate I/O pins that also

serve as data inputs in the parallel load mode. Q 0 and Q 7 are

also brought out on other pins for expansion in serial shifting

of longer words.

A LOW signal on MR overrides the Select and CP inputs and

resets the flip-flops. All other state changes are initiated by

the rising edge of the clock. Inputs can change when the

clock is in either state provided only that the recommended

setup and hold times, relative to the rising edge of CP, are

observed.

A HIGH signal on either OE 1 or OE 2 disables the TRI-STATE

buffers and puts the I/O pins in the high impedance state. In

this condition the shift, hold, load and reset operations can

still occur. The TRI-STATE buffers are also disabled by HIGH

signals on both S 0 and S 1 in preparation for a parallel load

operation.

Truth Table

Inputs

Response

MR S 1 S 0 CP

L X X X Asynchronous Reset;

Q 0 –Q 7 = LOW

HHH N Parallel Load; I/O n

Q n

H N Shift Right; DS 0

Q 0 ,

Q 0 ® Q 1 , etc.

HHL N Shift Left, DS 7

Q 7 ,

Q 7

Q 6 , etc.

Hold

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW-to-HIGH Transition

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Logic Diagram

DS100252-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V CC )

Recommended Operating

Conditions

Supply Voltage (V CC )

(Unless Otherwise Specified)

’AC

−0.5V to +7.0V

2.0V to 6.0V

DC Input Diode Current (I IK )

V I = −0.5V

’ACT

4.5V to 5.0V

−20 mA

Input Voltage (V I )

0VtoV CC

V I = V CC +0.5V

+20 mA

Output Voltage (V O )

0VtoV CC

DC Input Voltage (V I )

−0.5V to V CC +0.5V

Operating Temperature (T A )

54AC/ACT

DC Output Diode Current (I OK )

V O = −0.5V

−55˚C to +125˚C

−20 mA

Minimum Input Edge Rate (

V O = V CC +0.5V

+20 mA

’AC Devices

V IN from 30% to 70% of V CC

V CC @ 3.3V, 4.5V, 5.5V

DC Output Voltage (V O )

−0.5V to V CC +0.5V

DC Output Source or Sink Current

(I O )

125 mV/ns

± 50 mA

Minimum Input Edge Rate (

DC V CC or Ground Current

Per Output Pin (I CC or I GND )

’ACT Devices

V IN from 0.8V to 2.0V

V CC @ 4.5V, 5.5V 125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. Obviously the databook specifications should be

met, without exception, to ensure that the system design is reliable over its

power supply, temperature, and output/input loading variables. National does

not recommend operation of FACT ® circuits outside databook specifications.

± 50 mA

Storage Temperature (T STG )

−65˚C to +150˚C

Junction Temperature (T J )

CDIP

175˚C

DC Electrical Characteristics

For ’AC Family Devices

54AC

Symbol

Parameter

V CC

T A =

Units

Conditions

(V)

−55˚C to +125˚C

Guaranteed Limits

V OUT = 0.1V

V IH

Minimum High Level

3.0

2.1

Input Voltage

4.5

3.15

or V CC − 0.1V

5.5

3.85

V OUT = 0.1V

V IL

Maximum Low Level

3.0

0.9

Input Voltage

4.5

1.35

or V CC − 0.1V

5.5

1.65

I OUT = −50 µA

V OH

Minimum High Level

3.0

2.9

Output Voltage

4.5

4.4

5.5

5.4

(Note 2)

V IN = V IL or V IH

I OH = −12 mA

3.0

2.4

I OH = −24 mA

4.5

3.7

I OH = −24 mA

5.5

4.7

I OUT = 50 µA

V OL

Maximum Low Level

3.0

0.1

Output Voltage

4.5

0.1

5.5

0.1

(Note 2)

V IN = V IL or V IH

I OH = 12 mA

3.0

0.50

I OH = 24 mA

4.5

0.50

I OH = 24 mA

5.5

0.50

± 1.0

V I = V CC , GND

I IN

Maximum Input

5.5

µA

Leakage Current

Note 2: All outputs loaded; threshold on input associated with output under test.

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DC Electrical Characteristics

For ’AC Family Devices

54AC

Symbol

Parameter

V CC

T A =

Units

Conditions

(V)

−55˚C to +125˚C

Guaranteed Limits

(Note 4)

I OLD

Minimum Dynamic

5.5

V OLD = 1.65V Max

I OHD

Output Current

5.5

−50

V OHD = 3.85V Min

I CC

Maximum Quiescent

5.5

80.0

µA

V IN = V CC

Supply Current

or GND

I OZT

Maximum I/O

V I (OE) = V IL ,V IH

± 5.5

Leakage Current

5.5

µA

V I = V CC , GND

V O = V CC , GND

Note 3: All outputs loaded; threshold on input associated with output under test.

Note 4: Maximum test duration 20 ms, one output loaded at a time.

Note 5: I IN and I CC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V CC .

I CC for 54AC @ 25˚C is identical to 74AC @ 25˚C.

DC Electrical Characteristics

For ’ACT Family Devices

54ACT

T A =

Symbol

Parameter

V CC

Units

Conditions

(V)

−55˚C to +125˚C

Guaranteed Limits

V OUT = 0.1V

V IH

Minimum High Level

4.5

2.0

Input Voltage

5.5

2.0

or V CC − 0.1V

V OUT = 0.1V

V IL

Maximum Low Level

3.0

0.8

Input Voltage

4.5

0.8

or V CC − 0.1V

I OUT = −50 µA

V OH

Minimum High Level

4.5

4.4

5.5

5.4

(Note 7)

V IN = V IL or V IH

I OH = −24 mA

4.5

3.70

I OH = −24 mA

5.5

4.70

I OUT = 50 µA

V OL

Maximum Low Level

4.5

0.1

Output Voltage

5.5

0.1

(Note 7)

V IN = V IL or V IH

4.5

0.50

I OL = 24 mA

5.5

0.50

I OL = 24 mA

± 1.0

I IN

Maximum Input

5.5

µA

V I = V CC , GND

Leakage Current

V I = V CC − 2.1V

I CCT

Maximum I CC /Input

5.5

1.6

(Note 8)

V OLD = 1.65V Max

I OLD

Minimum Dynamic

5.5

V OHD = 3.85V Min

I OHD

Output Current

5.5

−50

V IN = V CC

I CC

Maximum Quiescent

5.5

80.0

µA

Supply Current

or GND

V I (OE) = V IL ,V IH

I OZT

Maximum I/O

± 5.0

V I = V CC , GND

V O = V CC , GND

Leakage Current

5.5

µA

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