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b a k e r ’ s b e s t
,,
By Bonnie Baker
 E ntry-level engineers know ADC topologies so well that dur-
selves at the DAC’s output as glitches.
The R2R-back DAC, like the MDAC,
typically has excellent low noise, INL,
and DNL performance, with medium
settling-time capability.
The string DAC suits portable-in-
strumentation, closed-loop-servo-con-
trol, process-control, and data-acquisi-
tion systems ( Figure 1c ). The figure
shows a model of a 3-bit-resistor string
DAC. Here the digital-input code is
101b, which decodes to 5/8V REF . The
output-stage buffer isolates the inter-
nal resistive elements from the output
load. The string DAC is a low-power
option that guarantees monotonicity
with good DNL performance across
the input-code range. The glitch en-
ergy is typically lower than that with
other types of DACs; howe ver, the
INL performance is sensitive to chip
layout and depends on resistive-array
matching. The noise of string DACs
is also relatively high and again de-
pends on the resistive-string-array
impedanc e. EDN
ing interviews, most job seekers can draw and explain fun-
damental block diagrams. The same situation does not hold
true for DAC topologies. In this case, applicants can tell me
only the basics: Digital goes in, and analog comes out.
DACs you find in high-precision
control-loop applications typically use
the R2R (resistor ladder) MDAC (mul-
tiplying DAC, Figure 1a ). This archi-
tecture can achieve high-voltage out-
put. MDAC manufacturers can design
high-resolution (16-bit) devices with
61 LSB INL (integral-nonlinear) and
DNL (differential-nonlinear) specifica-
tions. MDACs require an external cur-
rent-to-voltage operational amplifier
but exhibit fast settling time (less than
0.3 msec) with a multiplying bandwidth
that can be greater than 10 MHz.
The R2R-back DAC is most appro-
priate for industrial applications ( Fig-
ure 1b ). With this DAC, each update
involves switching the 2R legs to ei-
ther the voltage reference high, V REF-H
or the voltage reference low, V REF-L .
This architecture can be relatively sim-
ple to manufacture. The R2R architec-
ture has a parallel data-input bus. For
devices with a serial interface, the mul-
tibit DAC uses a serial-to-parallel reg-
ister internally before latching the da-
ta to the DAC. In either case, gate-
switch timing skews manifest them-
Bonnie Baker is a senior applications
engineer at Texas Instruments. You can
reach her at bonnie@ti.com.
V REF
R
R
R
V REF
R
7/8V REF
2R
2R
2R
2R
2R
R FB
1
LEAST-
SIGNIFICANT
BIT
R
MOST-
SIGNIFICANT
BIT
EXTERNAL
OP AMP
6/8V REF
0
1
R
0
5/8V REF
1
R
4/8V REF
0
(a)
1
R
V OUT
ANALOG
OUTPUT
3/8V REF
0
1
= V REF (b i /2 i )
R
R
R
R
V FB
V OUT
2/8V REF
0
1
2R
2R
2R
2R 2R
R
LEAST-
SIGNIFICANT
BIT
MOST-
SIGNIFICANT
BIT
1/8V REF
0
1
R
0V
0
V REF-H
V REF-L
LEAST-
SIGNIFICANT
BIT
1
0
MOST-
SIGNIFICANT
BIT
1
(b)
(c)
Figure 1 Typical topologies of popular DACs include R2R-multiplying (a), R2R-back (b), and resistor-string (c) architectures.
34 EDN | january 18, 2007
Comparing DAC architectures
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