EEWebPULSE_2012_i0047.pdf

EE Web

PULSE

EE Web.com

Issue 47

May 22, 2012

Michael

McNamara

Cadence

Electrical Engineering Community

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TABLE OF CONTENTS

Michael McNamara

CADENCE

Interview with Michael McNamara - Vice President and General Manager of

System Level Design

TLM-Drive Design and Vertification

Using Cadence ®

BY MICHAEL MCNAMARA

How Cadence is pioneering the transition to transaction level modeling for faster design and

verification times, esier IP and fewer bugs.

Featured Products

React Quickly or Feel The Pain

BY DAVE LACEY WITH XMOS

Response time plays a crucial role in real-time efficacy in system programming.

Advanced Complementary Bipolar

Processes on Bonded-SOI Substrates

BY STEPHEN PARKS, RICK JEROME, JOSHUA BAYLOR,

AND MICHAEL SUN WITH INTERSIL

BSOI substrates offer a number of important advantages to ensure high-level performance in

semiconductors.

RTZ - Return to Zero Comic

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INTERVIEW

ichael

cNamara

Cadence

Can you tell us about your

work experience/ history

before becoming the Vice

President of System Level

Design at Cadence?

After graduating from Cornell

University in 1985 with a Master’s

Degree in computer architecture

from the Electrical Engineering

school, I worked in the defense

industry, building computer systems

designed to find submarines (think

Hunt for Red October). As the

cold war ended, I moved into the

commercial sector, first building

computer systems designed to

help find oil at Cydrome in 1987;

and then at Ardent Computer in

1989 building systems optimized

for the MRI machines – finding

torn ligaments. My work was in

specifying & modeling the systems;

verifying the implementation, and

bringing up the operating systems

on these diverse computerized

systems.

Michael McNamara - Vice President and General Manager of System Level Design

We used Verilog simulation to

design and verify the computer

systems we were developing, and

the commercial tools available at

the time ran far too slowly to be

useful for our needs. So a number

of us from Ardent got together in

1991 to form Chronologic to write a

compiler for the Verilog language –

VCS. I served as VP of Engineering,

and we delivered a 10x speedup in

verification speed over the Verilog-

XL tool from Cadence. Regression

tests that took a week could be

completed overnight; greatly

increasing the productivity of the

integrated chip design process.

Will you tell us about starting

Chronologic in the 90’s,

bringing VCS to the world, and

then later co-founding SureFire

Veriication, improving the

state of the veriication

software?

After selling Chronologic to

Viewlogic in 1994 (and then

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INTERVIEW

to Synopsys), a number of us

recognized the next barrier to

productivity was in the lack of

automation in verification. So we

founded SureFire Verification in

1996 to develop tools for measuring

test coverage, performing static

verification as well as automatic test

generation. We merged SureFire

into Verisity in 1999, and together

went public in 2001. Cadence

acquired Verisity in 2005.

around at your team. Ask what tasks

seem to be consuming increasing

percentages of your time. What

is the emerging bottleneck in your

job? What would it take to reduce

the bottleneck? Is there a company

you could start to address reducing

this bottleneck?

The second technology we

developed is the Cadence

Virtual System Platform (VSP),

which is a set of tools enabling

rapid creation of programmer

view models of hardware, in the

SystemC language; the execution

and debug of embedded software

running on these models in a pure

virtual platform environment, or

on any mixture of execution where

some blocks are represented as

RTL. The RTL can run simulated

on a workstation or accelerated in

the Cadence Virtual Computing

Platform known as Palladium PXP.

What has been your favorite

project?

My most enjoyable project was

building the Chronologic Verilog

Compiled Simulator (VCS). In less

than 12 months we built a tool that

delivered a 10x improvement in

simulation performance, and won

business at Sun Microsystems,

Silicon Graphics and AMD.

What have been some of your

inluences that have helped

you get to where you are

today?

The inexorable pace of complexity

increase driven by Moore’s

law provides the commercial

opportunity to successively

optimize each step of the design

and verification process, as they

become bottlenecks. In the 70’s,

it became too difficult to layout

transistors by hand; so the industry

developed place and route tools.

In the 80’s, it became too slow to

capture logic designs as networks

of gates; so the industry developed

RTL simulation and synthesis. In

the 90’s, it became too slow to

write tests by hand to verify these

RTL designs, so we developed

automatic test bench systems.

Where is this type of

technology used?

Quite a number of companies are

using CtoS and VSP; recent press

releases document the success that

companies like Casio and Renesas

have had with C-to-Silicon, and that

Xilinx has had with the Cadence

Virtual System Platform. The VSP

was even awarded the 2012 ACE

award as the most significant

software product of the year.

What are you currently

working on?

I manage the teams at Cadence

which are developing the

methodologies and tools to improve

the efficiency of System Level

Design. System Level Design is

what people do before they start

into today’s RTL design process,

where they use the familiar Verilog

and VHDL languages for design,

and SystemVerilog and Specman

for verification.

Will you tell us about linking

virtual prototypes to high-level

synthesis?

The astute reader (and many of

my customers) quickly notices that

C-to-Silicon and VSP both accept

as input models of the hardware

which are written in the SystemC

language, and naturally ask if they

can feed, say the virtual model of

the image processing component

to C-to-Silicon, and hence get an

RTL implementation of the device.

The first technology we developed is

the Cadence C-to-Silicon Compiler

(CtoS), which is a high level

synthesis tool that enables engineers

to guide the automatic translation

of programs written in the C and

C++ programming languages into

very efficient RTL, controlling the

area, power and performance of

the resulting circuitry. This process

uses the IEEE standard SystemC

class library as the input format and

generates files in the IEEE Verilog

format as the output.

My colleagues and I have been

very successful by recognizing the

next bottleneck; developing tools

and methodologies to address the

bottleneck, and bringing these tools

to market properly timed to serve

the expanding needs.

Do you have any tricks up

your sleeve?

Occasionally back away from your

day-to-day activities and take a look

The answer is a guarded ‘yes,’ if

one plans for this dual-use up front.

In the general sense, the concern

of the person building a model of

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