W65C02S Datasheet.pdf
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W65C02S
January 14, 2009
W65C02S
8–bit Microprocessor
WDC reserves the right to make changes at any time without notice in order to improve design and supply
the best possible product. Information contained herein is provided gratuitously and without liability, to any
user. Reasonable efforts have been made to verify the accuracy of the information but no guarantee
whatsoever is given as to the accuracy or as to its applicability to particular uses. In every instance, it must
be the responsibility of the user to determine the suitability of the products for each application. WDC
products are not authorized for use as critical components in life support devices or systems. Nothing
contained herein shall be construed as a recommendation to use any product in violation of existing patents
or other rights of third parties. The sale of any WDC product is subject to all WDC Terms and Conditions of
Sales and Sales Policies, copies of which are available upon request.
Copyright
©
1981-2010 by The Western Design Center, Inc. All rights reserved, including the right of
reproduction, in whole, or in part, in any form.
2
TABLE OF CONTENTS
1
INTRODUCTION .......................................................................................................
6
1.1
F
EATURES OF THE
W65C02S ...........................................................................................................
6
2
FUNCTIONAL DESCRIPTION..................................................................................
7
2.1
I
NSTRUCTION
R
EGISTER
(IR)
AND
D
ECODE
........................................................................................
7
2.2
T
IMING
C
ONTROL
U
NIT
(TCU) ...........................................................................................................
7
2.3
A
RITHMETIC AND
L
OGIC
U
NIT
(ALU) .................................................................................................
7
2.4
A
CCUMULATOR
R
EGISTER
(A)...........................................................................................................
7
2.5
I
NDEX
R
EGISTERS
(X
AND
Y) .............................................................................................................
7
2.6
P
ROCESSOR
S
TATUS
R
EGISTER
(P) ..................................................................................................
7
2.7
P
ROGRAM
C
OUNTER
R
EGISTER
(PC) ................................................................................................
8
2.8
S
TACK
P
OINTER
R
EGISTER
(S)..........................................................................................................
8
3
PIN FUNCTION DESCRIPTION .............................................................................
10
3.1
A
DDRESS
B
US
(A0-A15) ................................................................................................................
10
3.2
B
US
E
NABLE
(BE) ..........................................................................................................................
10
3.3
D
ATA
B
US
(D0-D7) ........................................................................................................................
10
3.4
I
NTERRUPT
R
EQUEST
(IRQB)..........................................................................................................
10
3.5
M
EMORY
L
OCK
(MLB) ....................................................................................................................
10
3.6
N
ON
-M
ASKABLE
I
NTERRUPT
(NMIB) ...............................................................................................
10
3.7
N
O
C
ONNECT
(NC) .........................................................................................................................
10
3.8
P
HASE
2
I
N
(PHI2),
P
HASE
2
O
UT
(PHI2O)
AND
P
HASE
1
O
UT
(PHI1O) ..........................................
11
3.9
R
EAD
/W
RITE
(RWB) ......................................................................................................................
11
3.10
R
EADY
(RDY) ................................................................................................................................
11
3.11
R
ESET
(RESB) ..............................................................................................................................
11
3.12
S
ET
O
VERFLOW
(SOB) ...................................................................................................................
12
3.13
SYNC
HRONIZE WITH
O
P
C
ODE FETCH
(SYNC) ................................................................................
12
3.14
P
OWER
(VDD)
AND
G
ROUND
(VSS) ................................................................................................
12
3.15
V
ECTOR
P
ULL
(VPB) ......................................................................................................................
12
4
ADDRESSING MODES ..........................................................................................
15
4.1
A
BSOLUTE A
...................................................................................................................................
15
4.2
A
BSOLUTE
I
NDEXED
I
NDIRECT
(
A
,
X
) .................................................................................................
15
4.3
A
BSOLUTE
I
NDEXED WITH
X
A
,
X
......................................................................................................
15
4.4
A
BSOLUTE
I
NDEXED WITH
Y
A
,
Y
.....................................................................................................
16
4.5
A
BSOLUTE
I
NDIRECT
(
A
) .................................................................................................................
16
4.6
A
CCUMULATOR
A ...........................................................................................................................
16
4.7
I
MMEDIATE
A
DDRESSING
# ..............................................................................................................
16
4.8
I
MPLIED I
........................................................................................................................................
17
4.9
P
ROGRAM
C
OUNTER
R
ELATIVE R
....................................................................................................
17
4.10
S
TACK S
.........................................................................................................................................
17
4.11
Z
ERO
P
AGE ZP
...............................................................................................................................
17
4.12
Z
ERO
P
AGE
I
NDEXED
I
NDIRECT
(
ZP
,
X
) .............................................................................................
18
4.13
Z
ERO
P
AGE
I
NDEXED WITH
X
ZP
,
X
...................................................................................................
18
4.14
Z
ERO
P
AGE
I
NDEXED WITH
Y
ZP
,
Y
..................................................................................................
18
4.15
Z
ERO
P
AGE
I
NDIRECT
(
ZP
) ..............................................................................................................
18
4.16
Z
ERO
P
AGE
I
NDIRECT
I
NDEXED WITH
Y
(
ZP
),
Y
.................................................................................
19
5
OPERATION TABLES ............................................................................................
21
3
6
DC, AC AND TIMING CHARACTERISTICS ..........................................................
23
6.2
DC
C
HARACTERISTICS
TA
=
-40
°
C
TO
+85
°
C
(PLCC,
QFP)
TA=
0
°
C
TO
70
°
C
(DIP) ...................
24
6.3
AC
C
HARACTERISTICS
TA
=
-40
°
C
TO
+85
°
C
(PLCC,
QFP)
TA=
0
°
C
TO
70
°
C
(DIP) ...................
25
7
CAVEATS ...............................................................................................................
30
8
HARD CORE MODEL .............................................................................................
31
8.1
F
EATURES OF THE
W65C02S
H
ARD
C
ORE
M
ODEL
..........................................................................
31
9
SOFT CORE RTL MODEL .....................................................................................
31
9.1
W65C02
S
YNTHESIZABLE
RTL-C
ODE IN
V
ERILOG
HDL ..................................................................
31
10
ORDERING INFORMATION ...................................................................................
32
4
TABLE OF TABLES
TABLE 3-1 VECTOR LOCATIONS............................................................................................................
13
TABLE 3-2 PIN FUNCTION TABLE ..........................................................................................................
13
TABLE 4-1 ADDRESSING MODE TABLE ................................................................................................
20
TABLE 5-1 INSTRUCTION SET TABLE ...................................................................................................
21
TABLE 5-2 W65C02S OPCODE MATRIX.................................................................................................
22
TABLE 6-1 ABSOLUTE MAXIMUM RATINGS..........................................................................................
23
TABLE 6-2 DC CHARACTERISTICS ........................................................................................................
24
TABLE 6-3 AC CHARACTERISTICS .......................................................................................................
25
TABLE 6-4 OPERATION, OPERATION CODES AND STATUS REGISTER...........................................
27
TABLE 7-1 MICROPROCESSOR OPERATIONAL ENHANCEMENTS ...................................................
30
TABLE OF FIGURES
FIGURE 2-1 W65C02S INTERNAL ARCHITECTURE SIMPLIFIED BLOCK DIAGRAM ..
.........................
8
FIGURE 2-2 W65C02S MICROPROCESSOR PROGRAMMING MODEL.
................................................
9
FIGURE 3-1 W65C02S 40 PIN PDIP PINOUT..
........................................................................................
14
FIGURE 3-2 W65C02S 44 PIN PLCC PINOUT..
.......................................................................................
14
FIGURE 6-1 IDD VS VDD...
......................................................................................................................
24
FIGURE 6-2 F MAX VS VDD ..
..................................................................................................................
24
FIGURE 6-3 GENERAL TIMING DIAGRAM..
............................................................................................
26
5
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