w65c22.pdf

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W65C22S
May 27, 2010
W65C22
(W65C22N and W65C22S)
Versatile Interface Adapter (VIA)
Datasheet
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WDC reserves the right to make changes at any time without notice in order to improve design and supply
the best possible product. Information contained herein is provided gratuitously and without liability, to any
user. Reasonable efforts have been made to verify the accuracy of the information but no guarantee
whatsoever is given as to the accuracy or as to its applicability to particular uses. In every instance, it must
be the responsibility of the user to determine the suitability of the products for each application. WDC
products are not authorized for use as critical components in life support devices or systems. Nothing
contained herein shall be construed as a recommendation to use any product in violation of existing patents
or other rights of third parties. The sale of any WDC product is subject to all WDC Terms and Conditions of
Sales and Sales Policies, copies of which are available upon request.
Copyright © 1981-2010 by The Western Design Center, Inc. All rights reserved, including the right of
reproduction, in whole or in part, in any form.
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TABLE OF CONTENTS
1.   INTRODUCTION...................................................................................................... 7  
2.   W65C22 FUNCTION DESCRIPTION ...................................................................... 8  
2.1   Peripheral Data Ports ................................................................................................................ 8  
2.2   Data Transfer - Handshake Control ....................................................................................... 10  
2.3   Read Handshake Control. ....................................................................................................... 11  
2.4   Write Handshake Control. ....................................................................................................... 12  
2.5   Timer 1 Operation .................................................................................................................... 14  
2.6   Timer 1 One-Shot Mode .......................................................................................................... 17  
2.7   Timer 1 Free-Run Mode........................................................................................................... 18  
2.8   Timer 2 Operation .................................................................................................................... 19  
2.9   Timer 2 One-Shot Mode .......................................................................................................... 19  
2.10   Timer 2 Pulse Counting Mode ................................................................................................ 20  
2.11   Shift Register Operation ......................................................................................................... 20  
2.12   Shift Register Input Modes ..................................................................................................... 21  
2.12.1   Shift Register Disabled (000) ............................................................................................ 21  
2.12.2   Shift In - Counter T2 Control (001).................................................................................... 22  
2.12.3   Shift In - PHI2 Clock Control (010).................................................................................... 22  
2.12.4   Shift In - External CB1 Clock Control (011) ...................................................................... 23  
2.13   Shift Register Output Modes .................................................................................................. 23  
2.13.1   Shift Out - Free Running at T2 Rate (100)........................................................................ 23  
2.13.2   Shift Out - T2 Control (101) ............................................................................................... 24  
2.13.3   Shift Out - PHI2 Clock Control (110)................................................................................ 24  
2.13.4   Shift Out - External CB1 Clock Control (111) .................................................................. 25  
2.14   Interrupt Operation .................................................................................................................. 25  
3.   PIN FUNCTION DESCRIPTION ............................................................................ 28  
3.1   Peripheral Data Port A Control Lines (CA1, CA2) ................................................................ 29  
3.2   Peripheral Data Port B Control Lines (CB1, CB2) ................................................................ 29  
3.3   Chip Select (CS1, CS2B) ......................................................................................................... 29  
3.4   Data Bus (D0-D7) ..................................................................................................................... 30  
3.5   Interrupt Request (IRQB) ........................................................................................................ 30  
3.6   Peripheral Data Port A (PA0-PA7) .......................................................................................... 31  
3.7   Peripheral Data Port B (PB0-PB7) .......................................................................................... 33  
3.8   Phase 2 Internal Clock (PHI2) ................................................................................................. 35  
3.9   Reset (RESB)............................................................................................................................ 35  
3.10   Register Select (RS0-RS3) ...................................................................................................... 35  
3.11   RWB (Read/Write) .................................................................................................................... 35  
3.12   VDD and VSS............................................................................................................................ 35  
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4.   TIMING, AC AND DC CHARACTERISTICS ......................................................... 36  
4.1   W65C22 Absolute Maximum Ratings .................................................................................... 36  
4.2   DC Characteristics TA= -40 ° C to +85C ° ................................................................................. 37  
4.3   AC Characteristic TA=-40 ° C to + 85 ° C .................................................................................... 41  
4.4   Timing Diagrams ...................................................................................................................... 45  
5.   CAVEATS .............................................................................................................. 49  
5.1   Older Versions ......................................................................................................................... 49  
5.2   Shift Clock ................................................................................................................................ 49  
5.3   Bus Holding Pins ..................................................................................................................... 49  
5.4   Current Limiting ....................................................................................................................... 49  
6.   HARD CORE MODEL ........................................................................................... 50  
6.1   W65C22C vs. W65C22S ........................................................................................................... 50  
6.2   Chip Select ............................................................................................................................... 50  
6.3   W65C22C and W65C22S Timing ............................................................................................ 50  
7.   ORDERING INFORMATION.................................................................................. 51  
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Table of Figures
FIGURE 1-1 W65C22 INTERNAL ARCHITECTURE BLOCK DIAGRAM ................................................... 7  
FIGURE 2-1 READ HANDSHAKE OPERATION (PA ONLY) ................................................................... 11  
FIGURE 2-2 WRITE HANDSHAKE (PA AND PB)..................................................................................... 12  
FIGURE 3-1 W65C22 40 PIN PDIP PINOUT ............................................................................................ 28  
FIGURE 3-2 W65C22 44 PIN PLCC PINOUT ........................................................................................... 28  
FIGURE 3-3 W65C22N AND GTE - G65SC22 CMOS PORT A BUFFER (PA0-PA7, CA2) .................... 31  
FIGURE 4-1 READ TIMING ....................................................................................................................... 45  
FIGURE 4-2 WRITE TIMING...................................................................................................................... 45  
FIGURE 4-3 READ HANDSHAKE, PULSE MODE (CA2) .......................................................................... 46  
FIGURE 4-4 READ HANDSHAKE, HANDSHAKE MODE TIMING (CA2) ................................................ 46  
FIGURE 4-5 WRITE HANDSHAKE, PULSE MODE TIMING (CA2, CB2) ................................................ 46  
FIGURE 4-6 WRITE HANDSHAKE, HANDSHAKE MODE TIMING (CA2, CB2)...................................... 47  
FIGURE 4-7 PERIPHERAL DATA, INPUT LATCHING TIMING ................................................................. 47  
FIGURE 4-8 DATA SHIFT OUT, INTERNAL OR EXTERNAL SHIFT CLOCK TIMING............................ 47  
FIGURE 4-9 DATA SHIFT IN, INTERNAL OR EXTERNAL SHIFT CLOCK TIMING................................ 48  
FIGURE 4-10 EXTERNAL SHIFT CLOCK TIMING ................................................................................... 48  
FIGURE 4-11 PULSE COUNT INPUT TIMING ......................................................................................... 48  
FIGURE 4-12 TEST LOAD (ALL DYNAMIC PARAMETERS) ................................................................... 48  
FIGURE 5-1 HIGH RESISTANCE BUS HOLDING DEVICE ON THE W65C22S..................................... 49  
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