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INTEGRATED CIRCUITS
PCA9542
2-channel I
2
C multiplexer and interrupt
controller
Product specification
1999 Oct 07
Philips Semiconductors
Product specification
2-channel I
2
C multiplexer and interrupt controller
PCA9542
FEATURES
•
PIN CONFIGURATION
1-of-2 bi-directional translating multiplexer
•
Channel selection via I
2
C bus
A0
A1
A2
INT0
SD0
SC0
V
SS
1
2
3
4
5
6
7
14
V
DD
SDA
SCL
•
Operating supply voltage 2.5 to 3.6 V
13
•
12
Operating temperature range 0
°
C to 70
°
C
INT
11
•
Power-up with all multiplexer channels deselected
10
SC1
•
3 address pins, allowing up to 8 devices on the I
2
C bus
SD1
9
•
Low on resistance
INT1
8
DESCRIPTION
The PCA9542 is a 1-of-2 bi-directional translating multiplexer,
controlled via the I
2
C bus. The SCL/SDA upstream pair fans out to
two SCx/SDx downstream pairs, or channels. Only one SCx/SDx
channel is selected at a time, determined by the contents of the
programmable control register. Two interrupt inputs, one for each of
the SCx/SDx downstream pair, are provided. One interrupt output,
which acts as an AND of the two interrupt inputs, is provided. All I/O
pins are 5 V tolerant.
The pass gates of the multiplexer are constructed such that the V
DD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9542. This allows the use of different bus
voltages on each SCx/SDx pair, so that 3.3 V parts can
communicate with 5 V parts without any additional protection.
External pull-up resistors can pull the bus up to the desired voltage
level for this channel.
SW00475
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
A0
Address input 0
2
A1
Address input 1
3
A2
Address input 2
4
INT0
Interrupt input 0
5
SD0
Serial data 0
6
SC0
Serial clock 0
7
V
SS
Supply ground
8
INT1
Interrupt input 1
9
SD1
Serial data 1
10
SC1
Serial clock 1
11
INT
Interrupt output
12
SCL
Serial clock line
13
SDA
Serial data line
14
V
DD
Supply voltage
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
14-Pin Plastic TSSOP
0
°
C to +70
°
C
PCA9542PW DH
SOT402-1
1999 Oct 07
2
853–2177 22486
Philips Semiconductors
Product specification
2-channel I
2
C multiplexer and interrupt controller
PCA9542
BLOCK DIAGRAM
SC0
SC1
SD0
SD1
V
SS
POWER-ON
RESET
V
DD
A0
SCL
I
2
C-BUS
CONTROL
INPUT
FILTER
A1
SDA
A2
INT[0–1]
INT LOGIC
INT
SW00379
3
1999 Oct 07
Philips Semiconductors
Product specification
2-channel I
2
C multiplexer and interrupt controller
PCA9542
CHANNEL SELECTION
A SC0x/SD0x downstream pair, or channel, is selected by the
contents of the control register. This register is written after the
PCA9542 has been addressed. The 3 LSBs of the control byte are
used to determine which channel is to be selected. When a channel
is selected, the channel will become active after a stop condition has
been placed on the I
2
C bus. This ensures that all SCx/SDx lines will
be in a HIGH state when the channel is made active, so that no
false conditions are generated at the time of connection.
INTERRUPT HANDLING
The PCA9542 provides 2 interrupt inputs, one for each channel and
one open drain interrupt output. When an interrupt is generated by any
device, it will be detected by the PCA9542 and the interrupt output
will be driven LOW. The channel need not be active for detection of
the interrupt. A bit is also set in the control byte.
Bits 4 – 5 of the control byte correspond to channels 0 – 1 of the
PCA9542, respectively. Therefore, if an interrupt is generated by any
device connected to channel 1, then bit 5 will be set in the control
register. Likewise, an interrupt on any device connected to channel 0
would cause bit 4 of the control register to be set. The master can
then address the PCA9542 and read the contents of the control byte
to determine which channel contains the device generating the
interrupt. The master can then reconfigure the PCA9542 to select this
channel, and locate the device generating the interrupt and clear it.
It should be noted that more than one device can be providing an
interrupt on a channel, so it is up to the master to ensure that all
devices on a channel are interrogated for an interrupt.
CONTROL BYTE
SELECTED
CHANNEL
7
6
5
4
3
2
1
0
X
X
X
X
X
0
X
X
none
X
X
X
X
X
1
0
0
0 (SC0/SD0)
X
X
X
X
X
1
0
1
1 (SC1/SD1)
CONTROL REGISTER
7
6
5
4
3
2
1
0
INTERRUPTING
CHANNEL
7
6
5
4
3
2
1
0
X
X
INT1 INT0
X
B2
B1 B0
0
0
0
1
X
X
X
X
0 (SC0/SD0)
Interrupt bits
Channel select bits
0
0
1
0
X
X
X
X
1 (SC1/SD1)
(read only)
(read/write)
SW00477
POWER-ON RESET
During power-up, the control register defaults to all zeroes causing
all the channels to be deselected.
4
1999 Oct 07
Philips Semiconductors
Product specification
2-channel I
2
C multiplexer and interrupt controller
PCA9542
CHARACTERISTICS OF THE I
2
C-BUS
The I
2
C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 2).
Bit transfer
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see FIgure 1).
System configuration
A device generating a message is a transmitter: a device receiving
is the receiver. The device that controls the message is the master
and the devices which are controlled by the master are the slaves
(see Figure 3).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
SW00363
Figure 1. Bit transfer
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
SW00365
Figure 2. Definition of start and stop conditions
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
I
2
C
MULTIPLEXER
MASTER
TRANSMITTER
SLAVE
SW00366
Figure 3. System configuration
5
1999 Oct 07
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