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Application Note: CoolRunner™ CPLD
CoolRunner XPLA3 I
2
C Bus Controller
Implementation
R
XAPP333 (v1.0) January 5, 1999
Author: Anita Schreiber
Summary
This document details the VHDL implementation of an I
2
C controller in a Xilinx CoolRunner™
XPLA3 256 macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available,
making this the perfect target device for an I
2
C controller. The VHDL code described in this
document can be obtained by contacting Xilinx Technical Support.
Introduction
The I
2
C bus is a popular serial, two-wire interface used in many systems because of its low
overhead. The two-wire interface minimizes interconnections so ICs have fewer pins, and the
number of traces required on printed circuit boards is reduced. Capable of 100 KHz operation,
each device connected to the bus is software addressable by a unique address with a simple
Master/Slave protocol.
The CoolRunner I
2
C Controller design contains an asynchronous microcontroller (
C) interface
and provides I
2
C Master/Slave capability. It is intended to be used with a microcontroller (
µ
µ
C) or
microprocessor (
µ
P) as shown in
Figure 1
.
SDA
CoolRunner I2C Bus Controller
SCL
Address
Data
Control
I2C Master/
Slave
Interface
Microcontroller
Interface
Microcontroller
X315_01_091999
Figure 1: CoolRunner I
2
C Bus Controller
I
2
C Background
This section will describe the main protocol of the I
2
C bus. For more details and timing
diagrams, please refer to the I
2
C specification.
The I
2
C bus consists of two wires, serial data (SDA) and serial clock (SCL), which carry
information between the devices connected to the bus. The number of devices connected to
the same bus is limited only by a maximum bus capacitance of 400 pF. Both the SDA and SCL
lines are bidirectional lines, connected to a positive supply voltage via a pull-up resistor. When
the bus is free, both lines are High. The output stages of devices connected to the bus must
have an open-drain or open-collector in order to perform the wired-AND function.
Each device on the bus has a unique address and can operate as either a transmitter or
receiver. In addition, devices can also be configured as Masters or Slaves. A Master is the
device which initiates a data transfer on the bus and generates the clock signals to permit that
XAPP333 (v1.0) January 5, 1999
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CoolRunner XPLA3 I
2
C Bus Controller Implementation
R
transfer. Any other device that is being addressed is considered a Slave. The I
2
C protocol
defines an arbitration procedure that insures that if more than one Master simultaneously tries
to control the bus, only one is allowed to do so and the message is not corrupted. The
arbitration and clock synchronization procedures defined in the I
2
C specification are supported
by the CoolRunner I
2
C Controller.
Data transfers on the I
2
C bus are initiated with a START condition and are terminated with a
STOP condition. Normal data on the SDA line must be stable during the High period of the
clock. The High or Low state of the data line can only change when SCL is Low. The START
condition is a unique case and is defined by a High-to-Low transition on the SDA line while SCL
is High. Likewise, the STOP condition is a unique case and is defined by a Low-to-High
transition on the SDA line while SCL is High. The definitions of data, START, and STOP insure
that the START and STOP conditions will never be confused as data. This is shown in
Figure 2
.
SDA
MSB
SCL
1
2
3
7
8
9
S
P
ACK
Start
Condition
Stop
Condition
x315_10_101599
Figure 2: Data Transfer on the I
2
C Bus
Each data packet on the I
2
C bus consists of eight bits of data followed by an acknowledge bit
so one complete data byte transfer requires nine clock pulses. Data is transferred with the most
significant bit first (MSB). The transmitter releases the SDA line during the acknowledge bit and
the receiver of the data transfer must drive the SDA line low during the acknowledge bit to
acknowledge receipt of the data. If a Slave-receiver does not drive the SDA line Low during the
acknowledge bit, this indicates that the Slave-receiver was unable to accept the data and the
Master can then generate a STOP condition to abort the transfer. If the Master-receiver does
not generate an acknowledge, this indicates to the Slave-transmitter that this byte was the last
byte of the transfer.
Standard communication on the bus between a Master and a Slave is composed of four parts:
START, Slave address, data transfer, and STOP. The I
2
C protocol defines a data transfer
format for both 7-bit and 10-bit addressing. The implementation of the I
2
C controller in the Xilinx
CoolRunner CPLD supports the seven-bit address format. After the START condition, a Slave
address is sent. This address is seven bits long followed by an eighth-bit which is the read/write
bit. A "1" indicates a request for data (read) and a "0" indicates a data transmission (write). Only
the Slave with the calling address that matches the address transmitted by the Master
responds by sending back an acknowledge bit by pulling the SDA line Low on the ninth clock.
Once successful Slave addressing is achieved, the data transfer can proceed byte-by-byte as
specified by the read/write bit. The Master can terminate the communication by generating a
STOP signal to free the bus. However, the Master may generate a START signal without
generating a STOP signal first. This is called a repeated START.
CoolRunner I
2
C
Controller
The CoolRunner CPLD implementation of the I
2
C Controller supports the following features:
•
Microcontroller interface
•
Master or Slave operation
•
Multi-master operation
•
Software selectable acknowledge bit
•
Arbitration lost interrupt with automatic mode switching from Master to Slave
•
Calling address identification interrupt with automatic mode switching from Master to Slave
2
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XAPP333 (v1.0) January 5, 1999
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CoolRunner XPLA3 I
2
C Bus Controller Implementation
R
•
START and STOP signal generation/detection
•
Repeated START signal generation
•
Acknowledge bit generation/detection
•
Bus busy detection
•
100 KHz operation
Signal
Descriptions
The I/O signals of the CoolRunner I
2
C controller are described in
Ta b l e 1
. Pin numbers have
not been assigned to this design, this can be done to meet the system requirements of the
designer.
Table 1: CoolRunner I
2
C Controller Signal Description
Name
Direction
Description
SDA
Bidirectional
I
2
C Serial Data.
SCL
Bidirectional
I
2
C Serial Clock.
ADDR_BUS[23:0]
Input
µ
C Address Bus.
DATA_BUS[7:0]
Bidirectional
µ
C Data Bus
.
AS
Input
Address Strobe
. Active Low
C handshake signal
indicating that the address present on the address
bus is valid.
µ
DS
Input
Data Strobe.
Active Low
C handshake signal
indicating that the data present on the data bus is
valid or that the
µ
C is no longer driving the data bus
and the I
2
C Controller can place data on the data
bus.
µ
R_W
Input
Read/Write.
"1" indicates a read, "0" indicates a
write.
DTACK
Output
Data Transfer Acknowledge.
Active Low
C
handshake signal indicating that the I
2
C Controller
has placed valid data on the data bus for a read cycle
or that the I
2
C Controller has received the data on the
bus for a write cycle.
µ
IRQ
Output
Interrupt Request.
Active Low.
MCF
Output
Data Transferring Bit.
While one byte of data is
being transferred, this bit is cleared. It is set by the
falling edge of the ninth clock of a byte transfer. This
bit is used to signal the completion of a byte transfer
to the
µ
C.
CLK
Input
Clock.
This clock is input from the system. The
constants used in generating a 100 KHz SCL signal
assumes the frequency to be 1.832 MHz. Different
clock frequencies can be used, but the constants in
the VHDL source code must be recalculated.
XAPP333 (v1.0) January 5, 1999
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CoolRunner XPLA3 I
2
C Bus Controller Implementation
R
Block Diagram
The block diagram of the CoolRunner I
2
C Controller, shown in
Figure 3
was broken into two
major blocks, the
µ
C interface and the I
2
C interface.
µ
C Interface
ADDR_DECODE/Bus Interface
RESET
Status Register
MBSR
Control Register
MBCR
Address Register
MADR
Data Register
MBDR
SYS_CLK
I
2
C Header
Register
I
2
C Data
Register
Address
Compare
I
2
C Status
Register
START/
STOP
SCL
Generation
Arbitration and
START/STOP
Detection
Main State Machine
I2C Interface
X315_02_101599
Figure 3: CoolRunner I
2
C Controller
4
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XAPP333 (v1.0) January 5, 1999
1-800-255-7778
CoolRunner XPLA3 I
2
C Bus Controller Implementation
R
Microcontroller
Logic
The
C interface for the I
2
C controller design supports an asynchronous byte-wide bus
protocol. This protocol is the method in which the
µ
µ
C reads and writes the registers in the
design and is shown in
Figure 4
.
µ
C
I
2
C Controller
Address the Device
1. Set R/W to indicate direction of data transfer
2. Place Address on A23 - A1
3. Assert Address Strobe (AS)
4. Place data on D7 - D0 (if write)
5. Assert Data Strobe (DS)
Input the Data
1. Decode Address
2. Latch data on D7 - D0 (if write)
or Place data on D7 - D0 (if read)
3. Assert Data Transfer Acknowledge (DTACK)
Terminate Transfer
1. Latch data (if read)
2. Negate DS
3. Negate AS
4. Remove data from bus (if write)
Terminate the Cycle
1. Remove data from D7- D0 (if read)
2. Negate DTACK
Start Next Cycle
Figure 4:
µ
C Read/Write Protocol
Address Decode/Bus Interface Logic
The
C bus protocol is implemented in the CoolRunner I
2
C Controller in the state machine
shown in
Figure 5
.
µ
RESET
Asserted
IDLE
AS Asserted
RESET Negated
ADDRESS_MATCH
Negated
DS
Negated
ADDR
DS Asserted
ADDRESS_MATCH Asserted
AS Negated
DS Negated
DATA_TRS
AS Asserted
DS Asserted
ASSERT_DTACK
X315_03_010500
Figure 5:
µ
C Bus Interface State Machine
XAPP333 (v1.0) January 5, 1999
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