DOC0401.PDF

Features

• Compatible with MCS-51™ Products

• 8K Bytes of In-System Reprogrammable Downloadable Flash Memory

– SPI Serial Interface for Program Downloading

– Endurance: 1,000 Write/Erase Cycles

• 2K Bytes EEPROM

– Endurance: 100,000 Write/Erase Cycles

• 4.0V to 6V Operating Range

• Fully Static Operation: 0 Hz to 24 MHz

• Three-Level Program Memory Lock

• 256 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Three 16-bit Timer/Counters

• Nine Interrupt Sources

• Programmable UART Serial Channel

• SPI Serial Interface

• Low Power Idle and Power Down Modes

• Interrupt Recovery From Power Down

• Programmable Watchdog Timer

• Dual Data Pointer

• Power Off Flag

8-Bit

Microcontroller

with 8K Bytes

Flash

AT89S8252

Description

The AT89S8252 is a low-power, high-performance CMOS 8-bit microcomputer with

8K bytes of Downloadable Flash programmable and erasable read only memory and

2K bytes of EEPROM. The device is manufactured using Atmel’s high density nonvol-

atile memory technology and is compatible with the industry standard 80C51 instruc-

tion set and pinout. The on-chip Downloadable Flash allows the program memory to

be reprogrammed in-system through an SPI serial interface or by a conventional non-

volatile memory programmer. By combining a versatile 8-bit CPU with Downloadable

Flash on a monolithic chip, the Atmel AT89S8252 is a powerful microcomputer which

provides a highly flexible and cost effective solution to many embedded control appli-

cations.

The AT89S8252 provides the following standard features: 8K bytes of Downloadable

Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watch-

dog timer, two Data Pointers, three 16-bit timer/counters, a six-vector two-level inter-

rupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In

addition, the AT89S8252 is designed with static logic for operation down to zero fre-

quency and supports two software selectable power saving modes. The Idle Mode

stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt sys-

tem to continue functioning. The Power Down Mode saves the RAM contents but

freezes the oscillator, disabling all other chip functions until the next interrupt or hard-

ware reset.

The Downloadable Flash can be changed a single byte at a time and is accessible

through the SPI serial interface. Holding RESET active forces the SPI bus into a serial

programming interface and allows the program memory to be written to or read from

unless Lock Bit 2 has been activated.

0401D-A–12/97

4-105

Pin Configurations

PDIP

PLCC

(T2) P1.0

(T2 EX) P1.1

P1.2

P1.3

(SS) P1.4

(MOSI) P1.5

(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

(WR) P3.6

(RD) P3.7

XTAL2

XTAL1

GND

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

P2.4 (A12)

P2.3 (A11)

P2.2 (A10)

P2.1 (A9)

P2.0 (A8)

(MOSI) P1.5

(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

PQFP/TQFP

(MOSI) P1.5

(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

Pin Description

V CC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an

output port, each pin can sink eight TTL inputs. When 1s

are written to port 0 pins, the pins can be used as high-

impedance inputs.

Port 0 can also be configured to be the multiplexed low-

order address/data bus during accesses to external pro-

gram and data memory. In this mode, P0 has internal pul-

lups.

Port 0 also receives the code bytes during Flash program-

ming and outputs the code bytes during program verifica-

tion. External pullups are required during program verifica-

tion.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups.

The Port 1 output buffers can sink/source four TTL inputs.

When 1s are written to Port 1 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally being pulled low will source

current (I IL ) because of the internal pullups.

Some Port 1 pins provide additional functions. P1.0 and

P1.1 can be configured to be the timer/counter 2 external

count input (P1.0/T2) and the timer/counter 2 trigger input

(P1.1/T2EX), respectively.

4-106

AT89S8252

AT89S8252

Block Diagram

P0.0 - P0.7

P2.0 - P2.7

V CC

PORT 0 DRIVERS

PORT 2 DRIVERS

GND

EEPROM

RAM ADDR.

RAM

PORT 0

LATCH

PORT 2

LATCH

FLASH

ACC

STACK

POINTER

PROGRAM

ADDRESS

BUFFER

TMP2

TMP1

ALU

INCREMENTER

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PSW

PROGRAM

COUNTER

PSEN

ALE/PROG

EA / V PP

RST

TIMING

AND

CONTROL

INSTRUCTION

DPTR

WATCH

DOG

PORT 3

LATCH

PORT 1

LATCH

SPI

PORT

PROGRAM

LOGIC

OSC

PORT 3 DRIVERS

PORT 1 DRIVERS

P3.0 - P3.7

P1.0 - P1.7

4-107

Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured

as the SPI slave port select, data input/output and shift

clock input/output pins as shown in the following table.

Port Pin

Alternate Functions

Port Pin

Alternate Functions

P3.0

RXD (serial input port)

P3.1

TXD (serial output port)

P1.0

T2 (external count input to Timer/Counter 2),

clock-out

P3.2

INT0 (external interrupt 0)

P1.1

T2EX (Timer/Counter 2 capture/reload trigger

and direction control)

P3.3

INT1 (external interrupt 1)

P3.4

T0 (timer 0 external input)

P1.4

SS (Slave port select input)

P3.5

T1 (timer 1 external input)

P1.5

MOSI (Master data output, slave data input pin

for SPI channel)

P3.6

WR (external data memory write strobe)

P1.6

MISO (Master data input, slave data output pin

for SPI channel)

P3.7

RD (external data memory read strobe)

RST

Reset input. A high on this pin for two machine cycles while

the oscillator is running resets the device.

ALE/PROG

Address Latch Enable is an output pulse for latching the

low byte of the address during accesses to externa l mem-

ory. This pin is also the program pulse input (PROG) during

Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6

the oscillator frequency and may be used for external tim-

ing or clocking purposes. Note, however, that one ALE

pulse is skipped during each access to external data mem-

ory.

If desired, ALE operation can be disabled by setting bit 0 of

SFR location 8EH. With the bit set, ALE is active only dur-

ing a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high. Setting the ALE-disable bit has no

effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro-

gram memory.

When the AT89 S8252 i s executing code from external pro-

gram memory, PSE N is ac tivated twice each machine

cycle, except that two PSEN activations are skipped during

each access to external data memory.

EA/V PP

External Access Enable. EA must be strapped to GND in

order to enable the device to fetch code from external pro-

gram memory locations starting at 0000H up t o F FFFH.

Note, however, that if lock bit 1 is programmed, EA will be

inte rnally latched on reset.

EA should be strapped to V CC for internal program execu-

tions. This pin also receives the 12-volt programming

enable voltage (V PP ) during Flash programming when 12-

volt programming is selected.

P1.7

SCK (Master clock output, slave clock input pin

for SPI channel)

Port 1 also receives the low-order address bytes during

Flash programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups.

The Port 2 output buffers can sink/source four TTL inputs.

When 1s are written to Port 2 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 2 pins that are externally being pulled low will source

current (I IL ) because of the internal pullups.

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX @

DPTR). In this application, Port 2 uses strong internal pul-

lups when emitting 1s. During accesses to external data

memory that use 8-bit addresses (MOVX @ RI), Port 2

emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some

control signals during Flash programming and verification.

Port 3

Port 3 is an 8 bit bidirectional I/O port with internal pullups.

The Port 3 output buffers can sink/source four TTL inputs.

When 1s are written to Port 3 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 3 pins that are externally being pulled low will source

current (I IL ) because of the pullups.

Port 3 also serves the functions of various special features

of the AT89S8252, as shown in the following table.

Port 3 also receives some control signals for Flash pro-

gramming and verification.

4-108

AT89S8252

AT89S8252

XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Special Function Registers

A map of the on-chip memory area called the Special Func-

tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc-

cupied addresses may not be implemented on the chip.

Read accesses to these addresses will in general return

random data, and write accesses will have an indeterminate

effect.

Table 1. AT89S8252 SFR Map and Reset Values

0F8H

0FFH

0F0H

00000000

0F7H

0E8H

0EFH

0E0H

ACC

00000000

0E7H

0D8H

0DFH

0D0H

PSW

00000000

SPCR

000001XX

0D7H

0C8H

T2CON

00000000

T2MOD

XXXXXX00

RCAP2L

00000000

RCAP2H

00000000

TL2

00000000

TH2

00000000

0CFH

0C0H

0C7H

0B8H

XX000000

0BFH

0B0H

11111111

0B7H

0A8H

0X000000

SPSR

00XXXXXX

0AFH

0A0H

11111111

0A7H

98H

SCON

00000000

SBUF

XXXXXXXX

9FH

90H

11111111

WMCON

00000010

97H

88H

TCON

00000000

TMOD

00000000

TL0

00000000

TL1

00000000

TH0

00000000

TH1

00000000

8FH

80H

11111111

00000111

DP0L

00000000

DP0H

00000000

DP1L

00000000

DP1H

00000000

SPDR

XXXXXXXX

PCON

0XXX0000

87H

4-109

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