tiny28s.pdf

Features

• Utilizes the AVR ® RISC Architecture

• AVR – High-performance and Low-power RISC Architecture

– 90 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General-purpose Working Registers

– Up to 4 MIPS Throughput at 4 MHz

• Nonvolatile Program Memory

– 2K Bytes of Flash Program Memory

– Endurance: 1,000 Write/Erase Cycles

– Programming Lock for Flash Program Data Security

• Peripheral Features

– Interrupt and Wake-up on Low-level Input

– One 8-bit Timer/Counter with Separate Prescaler

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– Built-in High-current LED Driver with Programmable Modulation

• Special Microcontroller Features

– Low-power Idle and Power-down Modes

– External and Internal Interrupt Sources

– Power-on Reset Circuit with Programmable Start-up Time

– Internal Calibrated RC Oscillator

• Power Consumption at 1 MHz, 2V, 25 ° C

– Active: 3.0 mA

– Idle Mode: 1.2 mA

– Power-down Mode: <1 µA

• I/O and Packages

– 11 Programmable I/O Lines, 8 Input Lines and a High-current LED Driver

– 28-lead PDIP, 32-lead TQFP, and 32-pad MLF

• Operating Voltages

– V CC : 1.8V - 5.5V for the ATtiny28V

– V CC : 2.7V - 5.5V for the ATtiny28L

• Speed Grades

– 0 - 1.2 MHz for the ATtiny28V

– 0 - 4 MHz For the ATtiny28L

8-bit

Microcontroller

with 2K Bytes of

Flash

ATtiny28L

ATtiny28V

Summary

Pin Configurations

PDIP

TQFP/MLF

RESET

PD0

PD1

PD2

PD3

PD4

VCC

GND

XTAL1

XTAL2

PD5

PD6

PD7

(AIN0) PB0

PA0

PA1

PA3

PA2 (IR)

PB7

PB6

GND

VCC

PB5

PB4 (INT1)

PB3 (INT0)

PB2 (T0)

PB1 (AIN1)

PD3

PD4

VCC

GND

XTAL1

XTAL2

PB7

PB6

GND

VCC

PB5

Rev. 1062ES–10/01

Note: This is a summary docum e nt. A complete document is

ava il a bl e on ou r we b si te at www.atmel.com .

Description

The ATtiny28 is a low-power CMOS 8-bit microcontroller based on the AVR RISC archi-

tecture. By executing powerful instructions in a single clock cycle, the ATtiny28 achieves

throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize

power consumption versus processing speed. The AVR core combines a rich instruction

set with 32 general-purpose working registers. All the 32 registers are directly con-

nected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be

accessed in one single instruction executed in one clock cycle. The resulting architec-

ture is more code efficient while achieving throughputs up to ten times faster than

conventional CISC microcontrollers.

Block Diagram

Figure 1. The ATtiny28 Block Diagram

VCC

XTAL1

XTAL2

8-BIT DATA BUS

INTERNAL

CALIBRATED

OSCILLATOR

INTERNAL

OSCILLATOR

GND

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

RESET

PROGRAM

FLASH

HARDWARE

STACK

MCU CONTROL

INSTRUCTION

GENERAL

PURPOSE

REGISTERS

TIMER/

COUNTER

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

STATUS

HARDWARE

MODUL A TOR

PROGRAMMING

LOGIC

DATA REGISTER

PORTB

DATA REGISTER

PORTD

DATA DIR

REG. PORTD

DATA REGISTER

PORTA

PORTA CONTROL

PORTB

PORTD

PORTA

The ATtiny28 provides the following features: 2K bytes of Flash, 11 general-purpose I/O

lines, 8 input lines, a high-current LED driver, 32 general-purpose working registers, an

8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with

internal oscillator and 2 software-selectable power-saving modes. The Idle Mode stops

the CPU while allowing the timer/counter and interrupt system to continue functioning.

The Power-down mode saves the register contents but freezes the oscillator, disabling

all other chip functions until the next interrupt or hardware reset. The wake-up or inter-

ATtiny28L/V

1062ES–10/01

ATtiny28L/V

rupt on low-level input feature enables the ATtiny28 to be highly responsive to external

events, still featuring the lowest power consumption while in the power-down modes.

The device is manufactured using Atmel’s high-density, nonvolatile memory technology.

By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the Atmel

ATtiny28 is a powerful microcontroller that provides a highly flexible and cost-effective

solution to many embedded control applications. The ATtiny28 AVR is supported with a

full suite of program and system development tools including: macro assemblers, pro-

gram debugger/simulators, in-circuit emulators and evaluation kits.

Pin Descriptions

VCC

Supply voltage pin.

GND

Ground pin.

Port A (PA3..PA0)

Port A is a 4-bit I/O port. PA2 is output-only and can be used as a high-current LED

driver. At V CC = 2.0V, the PA2 output buffer can sink 25 mA. PA3, PA1 and PA0 are

bi-directional I/O pins with internal pull-ups (selected for each bit). The port pins are tri-

stated when a reset condition becomes active, even if the clock is not running.

Port B (PB7..PB0)

Port B is an 8-bit input port with internal pull-ups (selected for all Port B pins). Port B

pins that are externally pulled low will source current if the pull-ups are activated.

Port B also serves the functions of various special features of the ATtiny28 as listed on

page 38. If any of the special features are enabled, the pull-up(s) on the corresponding

pin(s) is automatically disabled. The port pins are tri-stated when a reset condition

becomes active, even if the clock is not running.

Port D (PD7..PD0)

Port D is an 8-bit I/O port. Port pins can provide internal pull-up resistors (selected for

each bit). The port pins are tri-stated when a reset condition becomes active, even if the

clock is not running.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

RESET

Reset input. An external reset is generated by a low level on the RESET pin. Reset

pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter

pulses are not guaranteed to generate a reset.

1062ES–10/01

Address

Nae

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F

SREG

page 11

$3E

Reserved

...

Reserved

$20

Reserved

$1F

Reserved

$1E

Reserved

$1D

Reserved

$1C

Reserved

$1B

PORTA

PORTA3

PORTA2

PORTA1

PORTA0

page 35

$1A

PACR

DDA3

PA2HC

DDA1

DDA0

page 35

$19

PINA

PINA3

PINA1

PINA0

page 36

$18

Reserved

$17

Reserved

$16

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

page 38

$15

Reserved

$14

Reserved

$13

Reserved

$12

PORTD

PORTD7

PORTD6

PORTD5

PORTD4

PORTD3

PORTD2

PORTD1

PORTD0

page 41

$11

DDRD

DDD7

DDD6

DDD5

DDD4

DDD3

DDD2

DDD1

DDD0

page 41

$10

PIND

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

page 41

$0F

Reserved

$0E

Reserved

$0D

Reserved

$0C

Reserved

$0B

Reserved

$0A

Reserved

$09

Reserved

$08

ACSR

ACD

ACO

ACI

ACIE

ACIS1

ACIS0

page 33

$07

MCUCS

PLUPB

WDRF

EXTRF

PORF

page 16

$06

ICR

INT1

INT0

LLIE

TOIE0

ISC11

ISC10

ISC01

ISC00

page 18

$05

IFR

INTF1

INTF0

TOV0

page 19

$04

TCCR0

FOV0

OOM01

OOM00

CS02

CS01

CS00

page 23

$03

TCNT0

Timer/Counter0 (8-bit)

page 24

ONTIM1

$02

MODCR

ONTIM4

ONTIM3

ONTIM2

ONTIM0

MCONF2

MCONF1

MCONF0

page 28

$01

WDTCR

WDTOE

WDE

WDP2

WDP1

WDP0

page 25

$00

OSCCAL

Oscillator Calibration Register

page 27

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all

bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work

with registers $00 to $1F only.

ATtiny28L/V

1062ES–10/01

ATtiny28L/V

Instruction Set Summary

Mnemonic

Operands

Description

Operation

Flags

# Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Add Two Registers

←

Rd + Rr

Z,C,N,V,H

ADC

Rd, Rr

Add with Carry Two Registers

←

Rd + Rr + C

Z,C,N,V,H

SUB

Rd, Rr

Subtract Two Registers

Rd ← Rd - Rr

Z,C,N,V,H

SUBI

Rd, K

Subtract Constant from Register

Rd ← Rd - K

Z,C,N,V,H

SBC

Rd, Rr

Subtract with Carry Two Registers

←

Rd - Rr - C

Z,C,N,V,H

SBCI

Rd, K

Subtract with Carry Constant from Reg.

←

Rd - K - C

Z,C,N,V,H

AND

Rd, Rr

Logical AND Registers

←

•

Z,N,V

ANDI

Rd, K

Logical AND Register and Constant

←

•

Z,N,V

Rd, Rr

Logical OR Registers

Rd ← Rd v Rr

Z,N,V

ORI

Rd, K

Logical OR Register and Constant

Rd ← Rd v K

Z,N,V

EOR

Rd, Rr

Exclusive OR Registers

←

⊕

Z,N,V

COM

One’s Complement

←

$FF - Rd

Z,C,N,V

NEG

Two’s Complement

←

$00 - Rd

Z,C,N,V,H

SBR

Rd, K

Set Bit(s) in Register

←

Rd v K

Z,N,V

CBR

Rd, K

Clear Bit(s) in Register

Rd ← Rd • (FFh - K)

Z,N,V

INC

Increment

Rd ← Rd + 1

Z,N,V

DEC

Decrement

←

Rd - 1

Z,N,V

TST

Test for Zero or Minus

←

•

Z,N,V

CLR

Clear Register

←

⊕

Z,N,V

SER

Set Register

←

$FF

None

BRANCH INSTRUCTIONS

RJMP

Relative Jump

PC ← PC + k + 1

None

RCALL

Relative Subroutine Call

←

PC + k + 1

None

RET

Subroutine Return

←

STACK

None

RETI

Interrupt Return

←

STACK

CPSE

Rd, Rr

Compare, Skip if Equal

if (Rd = Rr) PC

←

PC + 2 or 3

None

1/2

Rd, Rr

Compare

Rd - Rr

Z,N,V,C,H

CPC

Rd, Rr

Compare with Carry

Rd - Rr - C

Z,N,V,C,H

CPI

Rd, K

Compare Register with Immediate

Rd - K

Z N,V,C,H

SBRC

Rr, b

Skip if Bit in Register Cleared

if (Rr(b) = 0) PC

←

PC + 2 or 3

None

1/2

SBRS

Rr, b

Skip if Bit in Register is Set

if (Rr(b) = 1) PC

←

PC + 2 or 3

None

1/2

SBIC

P, b

Skip if Bit in I/O Register Cleared

if (P(b) = 0) PC

←

PC + 2 or 3

None

1/2

SBIS

P, b

Skip if Bit in I/O Register is Set

if (P(b) = 1) PC ← PC + 2 or 3

None

1/2

BRBS

s, k

Branch if Status Flag Set

if (SREG(s) = 1) then PC ← PC + k + 1

None

1/2

BRBC

s, k

Branch if Status Flag Cleared

if (SREG(s) = 0) then PC

←

PC + k + 1

None

1/2

BREQ

Branch if Equal

if (Z = 1) then PC

←

PC + k + 1

None

1/2

BRNE

Branch if Not Equal

if (Z = 0) then PC

←

PC + k + 1

None

1/2

BRCS

Branch if Carry Set

if (C = 1) then PC

←

PC + k + 1

None

1/2

BRCC

Branch if Carry Cleared

if (C = 0) then PC ← PC + k + 1

None

1/2

BRSH

Branch if Same or Higher

if (C = 0) then PC ← PC + k + 1

None

1/2

BRLO

Branch if Lower

if (C = 1) then PC

←

PC + k + 1

None

1/2

BRMI

Branch if Minus

if (N = 1) then PC

←

PC + k + 1

None

1/2

BRPL

Branch if Plus

if (N = 0) then PC

←

PC + k + 1

None

1/2

BRGE

Branch if Greater or Equal, Signed

if (N

⊕

V = 0) then PC

←

PC + k + 1

None

1/2

BRLT

Branch if Less than Zero, Signed

if (N ⊕ V = 1) then PC ← PC + k + 1

None

1/2

BRHS

Branch if Half-carry Flag Set

if (H = 1) then PC ← PC + k + 1

None

1/2

BRHC

Branch if Half-carry Flag Cleared

if (H = 0) then PC

←

PC + k + 1

None

1/2

BRTS

Branch if T-flag Set

if (T = 1) then PC

←

PC + k + 1

None

1/2

BRTC

Branch if T-flag Cleared

if (T = 0) then PC

←

PC + k + 1

None

1/2

BRVS

Branch if Overflow Flag is Set

if (V = 1) then PC

←

PC + k + 1

None

1/2

BRVC

Branch if Overflow Flag is Cleared

if (V = 0) then PC ← PC + k + 1

None

1/2

BRIE

Branch if Interrupt Enabled

if (I = 1) then PC ← PC + k + 1

None

1/2

BRID

Branch if Interrupt Disabled

if (I = 0) then PC

←

PC + k + 1

None

1/2

1062ES–10/01

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