e00b028.pdf

APPLICATION NOTE

The content of this note is based on information received from manufacturers in the electrical and electronics industries or

their representatives and does not imply practical experience by Elektor Electronics or its consultants.

XICOR X9258T, 9250T

Digital Controlled Potentiometers

By P Gareth Lloyd

pglloyd@iee.org

V CC

One of the most important aspects of

PA design is the biasing network. It

is important for the bias network to

reject RF power. Using high imped-

ance sources where possible accom-

plishes this. Where low impedance

sources are used, it is imperative to

maintain a good decoupling regime,

to maximize the transistor’s perfor-

mance.

At the FET drain (GaAs or

LDMOS), it is necessary to use a low

impedance bias supply. For transis-

tors not biased class A, the current

versus output power characteristic

is dynamic, and

any residual power supply imped-

ance will cause amplitude modula-

tion of the drain voltage.

Most commercial power ampli-

ﬁers have a bandwidth typically of a

maximum 10%, and therefore it is

possible to supply drain current

using a RF shorted quarter wave

section (which will transform to an

open circuit at the feed point). For

wideband applications (octave plus),

it is generally better to use an induc-

tor to feed bias to the drain.

The bias voltage may be fed onto

the transistor gate-matching net-

work via a surface mount resistor.

Typically, the resistance would be of

the order of a few hundred ohms to

ensure that minimal RF power leaks

through the resistor into the biasing

network. As the gate is extremely

high impedance and therefore the

current requirement is negligible, it

is possible to use the smallest pack-

age size readily available (typically

0603). This will reduce the effect of

any package parasitic resonance,

maximizing stability and perfor-

mance.

For LDMOS applications, thermal

compensation would be done using

either a simple analogue compensa-

tion scheme or using DSP to control

the XDCP. The gate voltage change

with respect to temperature (for con-

stant drain current) is around

–2mV.K -1 . Normally, the compensa-

tion constant would be a slightly dif-

ferent to this to maintain a constant

gain versus temperature response.

The biasing (quiescent current)

requirement varies between appli-

cations, but for a typical SCPA (sin-

gle carrier power ampliﬁer) a quies-

cent current tuning resolution of 1%

of Idq_opt is all that is needed.

Idq_opt is the typical bias condition,

which offers maximum dynamic gain

flatness and almost optimum two-

tone third order intermodulation dis-

tortion when a device is biased class

AB . This is easily achieved using an

8-bit XDCP, X9258T or X9250T with

256 wiper positions.

V CC

V (BIAS)

005128 - 11

Figure 1. XDCP-based wide range bias driver

for RF power ampliﬁers.

V CC

V (BIAS)

Application

Resolution

MCPA (Multi

Carrier Ampliﬁer)

8-bit or 2 x 6-bit

Large Dynamic

Conduction Angle Variation

2 x 6-bit

005128 - 12

SCPA

(Single Carrier Ampliﬁer) 6-bit or 8-bit

Figure 2. High resolution biasing of LDMOS

transistors.

Some applications, for example

MCPA (multicarrier power ampliﬁer)

Elektor Electronics

11/2000

APPLICATION NOTE

300

also be easily achieved

using two XDCPs and a

weighted summing net-

work at the buffer op-amp

input … effectively dou-

bling the bit resolution.

Two combined 6-bit

(64 positions) XDCPs can

achieve 12-bit (4096 posi-

tions) resolution.

By selecting the ratio

R1/R2 to be the same as

the number of tap points

(in this case 6 bits = 64

positions), it is possible to

achieve a dividing resolu-

tion of more than 4000

wiper positions. This

arrangement is more than

adequate to provide high

resolution biasing of

LDMOS devices, while giving maximum ﬂex-

ibility to bias the transistor in any class of

operation.

In the circuit shown in Figure 2 , The X9250

8-bit potentiometer will generally give the

required voltage resolution, especially when

the range of voltage outputs is conditioned.

This can be done by selecting upper and

lower limits for the high and low side of the

potentiometer.

Additionally, the op-amp buffer allows fur-

ther flexibility for range adjustment and the

introduction of an offset.

A typical LDMOS transistor requires a

change of approximately 2.5mV in gate volt-

age to effect a 1% change in drain current.

( Figure 3 ). It is therefore possible to use a sin-

gle 8-bit potentiometer to tune over a range

of 0.6V with 1% resolution. Using the 2 x 6-bit

potentiometer example highlighted earlier,

gives the potential for 1% resolution over a

10 V range, though normally the range would

be reduced to allow greater resolution.

On-chip memory is another feature incor-

porated in most of the XDCP range. This

allows the designer to load a set of four val-

ues for each potentiometer, and dynamically

assign the memory register to the poten-

tiometer at any point in time.

Generally, it is not necessary to use these

memory settings. The settings would nor-

250

200

150

100

V gg (Gate Voltage) / V

005128 - 13

Figure 3. LDMOS DC operating characteristic, drain current (% of Idq_opt) as a function of gate voltage.

may require finer bias control or

greater dynamic range to optimize

dynamic gain flatness. In some

cases, it may be desirable to actually

change the bias class (conduction

angle) completely, from A through

AB to B and possibly beyond.

As shown in Figure 1 , this can

- 1

- 2

- 3

- 4

- 5

- 6

10 3

10 4

10 5

10 6

10 7

10 8

TimeElapsed Since Manufacture (hours)

005128 - 14

Figure 4. Typical LDMOS drift characteristic.

11/2000

Elektor Electronics

APPLICATION NOTE

mally be stored and controlled by an external

processor and memory. Reloading new values

to the wiper register doesn’t result in any

spurious noise at the wiper.

This allows the PA bias setting to be

dynamically reprogrammed while ‘hot’ with

RF power, with no detrimental (or even

detectable) effect.

This is theoretically the worst time possi-

ble to change bias conditions on the transis-

tor, as any spikes on the bias supply could

result in large amounts of current drawn by

the transistor, enhanced by the RF power,

with possibly terminal consequences.

The memory settings are most likely to be

utilized for many power ampliﬁer design fea-

tures.

amplifier is undergoing test in the

factory; effectively burning the

device in, before delivery. Drift is

also proportional to the process cut-

off frequency. A typical drift charac-

teristic is shown in Figure 4 .

numerous applications where signif-

icant beneﬁt can be derived.

Summary

The XDCP offers the reliability and

flexibility of the DAC for the cost of

the mechanical potentiometer, giv-

ing the designer the rare opportunity

to make a win-win design improve-

ment.

The new software interface

allows easy prototyping of a

dynamic programming environment

with a minimum of hardware.

Flexibility of the XDCP is such

that it may also be used in the PA

periphery and control circuitry, not

only for biasing of transistors. Addi-

tionally, it may supersede the use of

the DAC in other cost critical RF sub-

systems.

Other RF Applications

– An Example

The XDCP can be used in a wide

variety of other RF applications. A

good example would be the vector

modulator.

The purpose of the vector modulator

is to manipulate an arbitrary signal,

allowing it’s amplitude and phase to

be varied in a controlled manner.

Recently, it has become a popular

method for complex gain adjustment

in linearized ampliﬁer systems, both

feed forward and predistortion.

The vector modulator consists of

a 3dB 90-degree hybrid, an in-phase

combiner, and two variable attenua-

tors, realised either with a pair of

mixers or two further 3-dB 90-degree

hybrids with diodes. Analysis of the

vector modulator is straightforward,

and is not detailed here.

The advantages of using a XDCP

over a DAC are the same as for the

power amplifier application. The

vector modulator example serves

only to highlight another of the

Digital thermal compensation

Thermal conditions are monitored by the sys-

tem microcontroller. This can use a look-up

table or algorithm to calculate the best oper-

ating point for the transistor. A preset list of

discrete values can be loaded into the memory

at production time, and loaded into the wiper

(005128-1)

Vg/Id drift compensation

LDMOS transistors suffer from performance

drift over time. The net effect is that a slightly

increased amount of gate voltage is required

to maintain a given drain current. LDMOS

processes are being reﬁned continually, and

current drift figures are typically 5% over 20

years. Most of this drift occurs while the

Xicor XDCP devices are available

through Kanda Systems Ltd., Unit

17-18, Glanyrafon Enterprise Park,

Aberystwyth, Ceredigion SY23 3JQ,

United Kingdom. Tel. (01970) 621030,

fax (01970) 621040.

Email sales@kanda.com ,

website http://www.kanda.com

CORRECTIONS &UPDATES

537 ‘Lite’ Computer

January & February 2000,

990054

The chip select lines address the

following memory ranges:

result in driver logic reflections

on K5. Conversely if using the

PCF8574 to drive the output of

K5, the dc logic level on K4 will

adversely affect the correct oper-

ation of the PCF8574.

HotKeys Keyboard (1 & 2)

April & May 2000, 002006

If hard to ﬁnd localy, the 8-MHz

ceramic resonator for this project

may be replaced by a quartz

crystal. The crystal wires are

then connected to the outer two

holes originally provided for the

resonator. Two 27pF capacitors

are connected between the crys-

tal wires and the central solder

pad.

The parts list in part 2 of the arti-

cle contains an error. The correct

type number of the caps for S1-

S16 is 707023-01.

3-Volts Car Adapter

July/August 2000, 000014

A capacitor (C2) of 100nF

(0.1 µF) should be ﬁtted between

R2 and ground.

CS0\

E000 - E7FF

CS1\

E800 - EFFF

CS2\

F000 - F7FF

EEDTS Pro Super Loco

Decoder

October 1999, 990071

The circuit of the decoder pro-

grammer, Figure 5, contains two

transistors ‘T2’. One of these

should be labelled ‘T3’. The cor-

rect type numbers of T2 and T3

are BD680, not BD560 as shown.

The value of C4 should be 2.2nF,

not 1 nF as shown.

PIC17C Processor Board

September 2000, 000061

Contrary to what is stated in the

Components List, the -A version

of the PIC processor is suitable

for use in this circuit. The

PIC17C756A is a ‘shrink-wrap’

version of the ‘C756. The stan-

dard PIC17C756 is no longer pro-

duced.

LCD

F800 - FFFF

8-bit I/O Port

July/August 2000, 994077

Due to logic level contention,

this interface can only operate

as an 8-bit input or an 8-bit out-

put. Using the PCF8574 to mon-

itor input logic levels on K4 will

Elektor Electronics

11/2000

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika: