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138908562 UNPDF
voltage boosting with inverters
033
U
1
4 U
in
2
in
(+2...+6V)
14
100p
100k
IC1 = 4069
IC2 ... = 74HCU04
IC5
IC1c
IC1b
IC1a
14
100
1
1
1
IC2
7
3 U
in
7
14
10
10
IC4
U
in
100
U
in
7
2 U
in
14
14
IC1
IC3
7
100
14
7
14
IC1
10
U
in
7
IC3
100
7
14
10
U
in
IC1 = 4069
IC2 ... = 74HCU04
IC4
100
(+2...+6V)
7
2 U
in
100k
100p
10
IC1c
IC1b
IC1a
14
14
10
1
1
1
IC2
IC5
7
100
7
3 U
in
994025 - 11
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G. Kleine
A ‘tree’ of inverters is highly suitable for boosting a voltage. That
in the diagram provides voltages that are whole multiples of the
input voltage by clock-driven charging of capacitors. The voltage
across the capacitors is added stage by stage to the input voltage.
Here, integrated circuits, IC 2 –IC 7 , each containing six inverters
are used. In each IC, except IC 2 , one of the inverters is connected
in series with the parallel combination of the other five.
Circuit IC 1 is configured as a 50 Hz oscillator that controls
inverting driver IC 2 . A 10 µF capacitor interlinks the outputs of
IC 2 and IC 3 . The bidirectional properties of the MOSFET output
of IC 3 ensure that the voltage across supply terminals 7 and 14 is
identical to the input voltage. The increased voltage, equal to 2V IN ,
is filtered by a 100 µF capacitor.
The outputs of IC 3 and IC 4 are also interlinked by a 10 µF
capacitor, and a similar process as just described takes place. This
continues up to the last IC on the tree.
The efficiency of the booster increases when the clock fre-
quency is lower than 50 Hz, but then the available output current
drops. If a current of 5 mA is drawn from the terminal at which
3V IN appears, the efficiency is about 90%. However, it drops to
around 75% when the current is increased to 15 mA.
The circuit can also be arranged as a voltage-inverting booster.
The ICs should then be arranged as shown in Figure 2.
[994025]
1
1
1
IC3, IC4, IC5.....
1
14
1
14
IC2
1
1
7
1
7
1
1
1
1
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Elektor Electronics
7-8/99
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138908562.001.png 138908562.002.png 138908562.003.png

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