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measurement interval
generator
011
15V
15V
15V
S2
CTRDIV10/
0
1
2
3
4
5
6
7
8
9
3
2
D
1
DEC
4
7
IC6
16
16
16
16
16
16
15
10
R5
CT=0
C4
C5
4017
1
IC1
IC2
IC3
IC4
IC5
IC6
100n
100n
14
&
5
8
8
8
8
8
8
+
6
T1
R3
R4
470k
13
9
11
CT
5
12
BC547C
*
see text
zie tekst
*
siehe Text
*
S1
10s; 1s; 100ms; 10ms; 1ms
*
voir texte
*
1kHz
100Hz
1Hz
0Hz1
C1
50p
10Hz
CTR14
7
0
1
2
3
4
5
6
7
8
9
3
2
0
1
2
3
4
5
6
7
8
9
3
2
0
1
2
3
4
5
6
7
8
9
3
2
0
1
2
3
4
5
6
7
8
9
3
2
3
4
5
6
7
8
9
CTRDIV10/
CTRDIV10/
CTRDIV10/
CTRDIV10/
C2
R2
2k2
X1
5
DEC
DEC
DEC
DEC
10
4
4
4
4
RX
!G
4
IC1
R1
7
7
7
7
39p
6
IC2
IC3
IC4
IC5
9
10
10
10
10
CX
14
4017
4017
4017
4017
+
14
1
14
1
14
1
14
1
C3
CT
13
&
&
&
&
11
RCX
+
5
+
5
+
5
+
5
15
13
6
13
6
13
6
13
6
56p
4.096MHz
1
11
12
9
9
9
9
CT=0
2
12
4060
15
11
15
11
15
11
15
11
CT=0
CT=0
CT=0
CT=0
3
13
12
12
12
12
CT
≥
5
CT
≥
5
CT
≥
5
CT
≥
5
994002 - 11
Design: K.-H. Lorenz
The purpose of this circuit is to generate a pulse with a predefined
duration when a button is pressed. It is especially well suited for
use as a timing window generator for a frequency counter. It uses
only inexpensive standard components and can be quickly put
together.
46
Elektor Electronics
7-8/99
In the schematic diagram, IC1 (a 4060) is a 14-stage binary counter
with an integrated oscillator. An inexpensive 4.096 MHz crystal is
used as the timing reference, which means that a 1 kHz signal
appears at the output (pin 1) after division by 2
14
. Following IC1 is
a series of decimal counters (IC2 through IC5, type 4017) that are
cascaded via their Carry Out outputs (pin 12). These counters pro-
duce reference frequencies of 100 Hz, 10 Hz, 1 Hz and 0.1 Hz.
The non-shorting rotary switch S1 selects one of the reference fre-
quencies and applies it to the clock input of an additional 4017. In
contrast to the other ICs of this type, its control inputs Reset and
/Enable (pins 15 and 13) are used dynamically. When pushbutton
S2 is pressed, the count is reset to zero. When S2 is released, the first
rising edge at pin 14 clocks the counter. The input signal, divided
by 2, appears at the Q1 output (pin 2). However, since Q3 (pin 7)
is connected to the /Enable input, the counter is disabled after the
first period of the output signal, so that only one pulse is gener-
ated. Depending on the input signal, this pulse has a length of 10 s,
1 s, 0.1 s, 0.01 s or 0.001 s.
A simple transistor buffer drives an LED that is illuminated for
the duration of the pulse. An additional, similar buffer stage at the
output would also be a good idea. The circuit should be powered
from a stabilized 15 V supply. It draws around 10 mA.
(994002-1)
Plik z chomika:
TirNaNog
Inne pliki z tego folderu:
bge.jpg
(22 KB)
detail1.htm
(5 KB)
detail10.htm
(6 KB)
detail12.htm
(12 KB)
e991018.pdf
(794 KB)
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