sg3525a.pdf

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REGULATING PULSE WIDTH MODULATORS
[
SG2525A
SG3525A
. 8 TO 35 V OPERATION
REGULATING PULSE WIDTH MODULATORS
. SEPARATE OSCILLATOR SYNC TERMINAL
. ADJUSTABLE DEADTIME CONTROL
. INTERNAL SOFT-START
. PULSE-BY-PULSE SHUTDOWN
. INPUT UNDERVOLTAGE LOCKOUT WITH
. LATCHING PWM TO PREVENT MULTIPLE
PULSES
HYSTERESIS
DIP16
16(Narrow)
. DUAL SOURCE/SINK OUTPUT DRIVERS
DESCRIPTION
The SG3525Aseries of pulse width modulator inte-
grated circuits are designed to offer improved per-
formance and lowered external parts count when
used in designing all types of switching power sup-
plies. The on-chip + 5.1 V reference is trimmed to ±
1 % and the input common-mode range of the error
amplifier includes the reference voltage eliminating
external resistors. A sync input to the oscillator al-
lows multiple units to be slaved or a single unit to be
synchronized to an external system clock. A single
resistor betweenthe C T andthe dischargeterminals
provide a wide range of dead time ad- justment.
Thesedevicesalso featurebuilt-insoft-startcircuitry
with only an external timing capacitor required. A
shutdownterminal controls both the soft-start circu-
ity and the output stages, providing instantaneous
turn off through the PWM latch with pulsed shut-
down, as well as soft-start recycle with longer shut-
down commands. These functions are also control-
led by an undervoltagelockout which keepsthe out-
puts off and the soft-start capacitor discharged for
sub-normal input voltages. This lockout circuitry in-
cludes approximately 500 mV of hysteresis for jitter-
free operation. Another feature of these PWM cir-
cuits is a latch following the comparator. Once a
PWM pulses has been terminated for any reason,
the outputs will remain off for the duration of the pe-
riod. The latch is reset with each clock pulse. The
output stages are totem-pole designs capable of
sourcing or sinking in excess of 200 mA. The
SG3525Aoutput stage features NOR logic, giving a
LOW output for an OFF state.
PIN CONNECTIONS AND ORDERING NUMBERS (top view)
Type
Plastic DIP
SO16
SG2525A
SG2525AN
SG2525AP
SG3525A
SG3525AN
SG3525AP
July 1998
1/12
. 5.1 V REFERENCE TRIMMED TO ± 1%
. 100 Hz TO 500 KHz OSCILLATOR RANGE
199641898.002.png
SG2525A-SG3525A
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V i
Supply Voltage
40
V
V C
Collector Supply Voltage
40
V
I OSC
Oscillator Charging Current
5
mA
I o
Output Current, Source or Sink
500
mA
I R
Reference Output Current
50
mA
I T
Current through C T Terminal
Logic Inputs
Analog Inputs
5
– 0.3 to + 5.5
– 0.3 to V i
mA
V
V
P tot
Total Power Dissipation at T amb =70
°
C
1000
mW
T j
Junction Temperature Range
– 55 to 150
C
T stg
Storage Temperature Range
– 65 to 150
C
T op
Operating Ambient Temperature : SG2525A
SG3525A
–25to85
0to70
C
°
C
THERMAL DATA
Symbol
Parameter
SO16
DIP16
Unit
R th j-pins
R th j-amb
R th j-alumina
Thermal Resistance Junction-pins
Max
50
80
°
C/W
Thermal Resistance Junction-ambient
Max
°
C/W
Thermal Resistance Junction-alumina (*)
Max
50
°
C/W
* Thermalresistance junction-alumina with the device soldered on themiddle ofan alumina supporting substrate measuring 15
×
20 mm ; 0.65 mm
thickness with infinite heatsink.
BLOCK DIAGRAM
2/12
°
°
°
199641898.003.png
SG2525A-SG3525A
ELECTRICAL CHARACTERISTICS
(V# i = 20 V, and over operating temperature, unless otherwise specified)
Symbol
Parameter
Test Conditions
SG2525A
SG3525A
Unit
Min. Typ. Max. Min. Typ. Max.
REFERENCE SECTION
V REF
Output Voltage
T j =25
°
C
5.05 5.1
5.15
5
5.1
5.2
V
D
V REF
Line Regulation
V i = 8 to 35 V
10
20
10
20
mV
D
V REF
Load Regulation
I L = 0 to 20 mA
20
50
20
50
mV
D
V REF /
D
T* Temp. Stability
Over Operating Range
20
50
20
50
mV
*
Total Output Variation Line, Load and
Temperature
5
5.2 4.95
5.25
V
Short Circuit Current
V REF =0T j =25
°
C
80
100
80
100
mA
*
Output Noise Voltage
10 Hz
3
f
3
10 kHz,
40
200
40
200
m
Vrms
T j =25
°
C
D
V REF * Long Term Stability
T j = 125
°
C, 1000 hrs
20
50
20
50
mV
OSCILLATOR SECTION * *
*,
•
Initial Accuracy
T j =25
°
C
±
2
±
6
±
2
±
6
%
*,
•
Voltage Stability
V i = 8 to 35 V
±
0.3
±
1
±
1
±
2
%
D
f/
D
T*
Temperature Stability
Over Operating Range
±
3
±
6
±
3
±
6
%
f MIN
Minimum Frequency
R T = 200 K
W
C T = 0.1
m
F
120
120
Hz
f MAX
Maximum Frequency
R T =2K
W
C T = 470 pF
400
400
KHz
Current Mirror
I RT = 2 mA
1.7
2
2.2
1.7
2
2.2
mA
*,
•
Clock Amplitude
3
3.5
3
3.5
V
*,
•
Clock Width
T j =25
°
C
0.3
0.5
1
0.3
0.5
1
m
s
Sync Threshold
1.2
2
2.8
1.2
2
2.8
V
Sync Input Current
Sync Voltage = 3.5 V
1
2.5
1
2.5
mA
ERROR AMPLIFIER SECTION (V CM = 5.1 V)
V OS
Input Offset Voltage
0.5
5
2
10
mV
I b
Input Bias Current
1
10
1
10
m
A
I os
Input Offset Current
1
1
m
A
DC Open Loop Gain
R L
.
10 M
W
60
75
60
75
dB
*
Gain Bandwidth
Product
G v = 0 dB T j =25
°
C1
2
1
2
z
*,
z
DC Transconduct.
30 K
W 3
R L
3
1M
W
1.1
1.5
1.1
1.5
ms
T j =25
°
C
Output Low Level
0.2
0.5
0.2
0.5
V
Output High Level
3.8
5.6
3.8
5.6
V
CMR
Comm. Mode Reject.
V CM = 1.5 to 5.2 V
60
75
60
75
dB
PSR
Supply Voltage
Rejection
V i = 8 to 35 V
50
60
50
60
dB
3/12
199641898.004.png
SG2525A-SG3525A
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Conditions
SG2525A
SG3525A
Unit
Min. Typ. Max. Min. Typ. Max.
PWM COMPARATOR
Minimum Duty-cycle
0
0
%
•
Maximum Duty-cycle
45
49
45
49
%
•
Input Threshold
Zero Duty-cycle
0.7
0.9
0.7
0.9
V
Maximum Duty-cycle
3.3
3.6
3.3
3.6
V
*
Input Bias Current
0.05
1
0.05
1
m
A
SHUTDOWN SECTION
Soft Start Current
V SD = 0 V, V SS V 500500
m
A
Soft Start Low Level
V SD = 2.5 V
0.4
0.7
0.4
0.7
V
Shutdown Threshold
To outputs, V SS = 5.1 V
T j =25
0.6
0.8
1
0.6
0.8
1
V
C
Shutdown Input Current V SD = 2.5 V
0.4
1
0.4
1
mA
*
Shutdown Delay
V SD = 2.5 V T j =25
°
C
0.2
0.5
0.2
0.5
m
s
OUTPUT DRIVERS (each output) (V C =20V)
Output Low Level
I sink = 20 mA
0.2
0.4
0.2
0.4
V
I sink = 100 mA
1
2
1
2
V
Output High Level
I source 0A
89
89
V
I source = 100 mA
17
18
17
18
V
Under-Voltage Lockout V comp and V ss = High
6
7
8
6
7
8
V
I C
Collector Leakage
V C = 35 V
200
200
m
A
t r *
Rise Time
C L = 1 nF, T j =25
°
C
100
600
100
600
ns
t f *
Fall Time
C L = 1 nF, T j =25
°
C
50
300
50
300
ns
TOTAL STANDBY CURRENT
I s
Supply Current
V i = 35 V
14
20
14
20
mA
* These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production.
• Tested at f osc = 40 KHz (R T = 3.6 K W ,C T = 10nF, R D =0 W ). Approximate oscillator frequency is defined by :
1
C T (0.7 R T +3R D )
. DC transconductance (g M ) relates to DC open-loop voltage gain (G v ) according to the following equation : G v =g M R L where R L is the resistance
from pin 9 to ground. The minimum g M specification is used to calculate minimum G v when the error amplifier output is loaded.
4/12
°
f=
199641898.005.png
SG2525A-SG3525A
TEST CIRCUIT
5/12
199641898.001.png

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