saa6579.pdf

INTEGRATED CIRCUITS

DATA SHEET

SAA6579

Radio Data System (RDS)

demodulator

Product speciﬁcation

Supersedes data of January 1994

File under Integrated Circuits, IC01

1997 Feb 24

Philips Semiconductors

Product speciﬁcation

Radio Data System (RDS) demodulator

SAA6579

FEATURES

GENERAL DESCRIPTION

Anti-aliasing filter (2nd order)

The integrated CMOS circuit SAA6579 is an RDS

demodulator. It recovers the additional inaudible RDS

information which is transmitted by FM radio broadcasting.

Integrated 57 kHz band-pass filter (8th order)

Reconstruction filter (2nd order)

The data signal RDDA and the clock signal RDCL are

provided as outputs for further processing by a suitable

decoder (microcomputer).

The operational functions of the device are in accordance

with the “CENELEC EN 50067”.

Clocked comparator with automatic offset compensation

57 kHz carrier regeneration

Synchronous demodulator for 57 kHz modulated RDS

signals

Selectable 4.332/8.664 MHz crystal oscillator with

variable dividers

Clock regeneration with lock on biphase data rate

Biphase symbol decoder with integrate and dump

functions

Differential decoder

Signal quality detector

Subcarrier output.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

MIN. TYP. MAX. UNIT

V DDA

analog supply voltage (pin 5)

3.6

5.0

5.5

V DDD

digital supply voltage (pin 12)

3.6

5.0

5.5

I tot

total supply current

V i(rms)

RDS input amplitude (RMS value; pin 4)

V OH

HIGH level output voltage for signals RDDA, RDCL, QUAL and T57 4.4

V OL

LOW level output voltage for signals RDDA, RDCL, QUAL and T57

0.4

T amb

operating ambient temperature

+85

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SAA6579

DIP16

plastic dual in-line package; 16 leads (300 mil); long body

SOT38-1

SAA6579T

SO16

plastic small outline package; 16 leads; body width 7.5 mm

SOT162-1

1997 Feb 24

Philips Semiconductors

Product speciﬁcation

Radio Data System (RDS) demodulator

SAA6579

BLOCK DIAGRAM

handbook, full pagewidth

47 pF

82 pF

4.332/8.664 MHz

+5 V

2.2 k W

0.1 µ F

OSCI

OSCO

V DDD

MPX

signal

MUX

ANTI-

ALIASING

FILTER

57 kHz

BANDPASS

(8th ORDER)

RECO N STRUCTION

FILTER

OSCILLATOR

AND

DIVIDER

QUALITY BIT

GENERATOR

QUAL

330 pF

SCOUT

560 pF

CIN

CLOC K ED

COMPARATOR

COSTAS LOOP

VARIABLE AND

FIXED DIVIDER

BIPHASE

SYMBOL

DECODER

DIFFE R ENTIAL

DECODER

RDDA

V DDA

SAA6579

RDCL

5 V

V P1

0.1

V ref

REFERENCE

VOLTAGE

CLOCK

REGENERATION

AND SYNC

TEST LOGIC AND O U TPUT

SELECTOR SWITCH

T57

2.2 µ F

MEH162

V SSA

MODE

TEST

V SSD

Via pin MODE two different crystal frequencies can be used.

MODE

CRYSTAL CLOCK

LOW

4.332 MHz

HIGH

8.664 MHz

Fig.1 Block diagram and application circuit.

1997 Feb 24

Philips Semiconductors

Product speciﬁcation

Radio Data System (RDS) demodulator

SAA6579

PINNING

SYMBOL

DESCRIPTION

QUAL

quality indication output

RDDA

RDS data output

V ref

reference voltage output (0.5V DDA )

MUX

multiplex signal input

V DDA

+5 V supply voltage for analog part

V SSA

ground for analog part (0 V)

CIN

subcarrier input to comparator

SCOUT

subcarrier output of reconstruction ﬁlter

MODE

oscillator mode/test control input

TEST

test enable input

V SSD

ground for digital part (0 V)

V DDD

+5 V supply voltage for digital part

OSCI

oscillator input

OSCO

oscillator output

T57

57 kHz clock signal output

RDCL

RDS clock output

handbook, halfpage

QUAL

RDCL

handbook, halfpage

QUAL

RDCL

RDDA

T57

RDDA

T57

V ref

MUX

OSCO

V ref

MUX

OSCO

OSCI

SAA6579

SAA6579T

V DDA

V DDD

V DDA

V DDD

V SSA

V SSD

V SSA

V SSD

CIN

TEST

CIN

TEST

SCOUT

MODE

SCOUT

MODE

MGD684

MGD685

Fig.2 Pin configuration.

Fig.3 Pin configuration.

1997 Feb 24

Philips Semiconductors

Product speciﬁcation

Radio Data System (RDS) demodulator

SAA6579

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); ground pins 6 and 11 connected together.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V DDA

analog supply voltage (pin 5)

V DDD

digital supply voltage (pin 12)

V n

voltage on all pins; grounds excluded

0.5

V DDX + 0.5 V

T stg

storage temperature

+150

T amb

operating ambient temperature

+85

V es

electrostatic handling for all pins except

pins 9 and 10

note 1

± 300

note 2

+1500

3000

series resistor.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 k

series resistor.

FUNCTIONAL DESCRIPTION

The overall data-channel-spectrum shaping of the

transmitter and the receiver is approximately 100% roll-off.

The Integrate and dump circuit performs an integration

over a clock period. This results in a demodulated and

valid RDS signal in form of biphase symbols being output

from the integrate and dump circuit. The final stages of

RDS data processing are the biphase symbol decoding

and the differential decoding. After synchronization by

data clock RDCL (pin 16) data appears on the RDDA

output (pin 2). The output of the biphase symbol decoder

is evaluated by a special circuit to provide an indication of

good data (QUAL = HIGH) or corrupt data (QUAL = LOW).

The SAA6579 is a demodulator circuit for RDS

applications. It contains a 57 kHz bandpass filter and a

digital demodulator to regenerate the RDS data stream out

of the multiplex signal (MPX).

Filter part

The MUX signal is band-limited by a second-order

anti-aliasing-filter and fed through a 57 kHz band-pass

filter (8th order band-pass filter with 3 kHz bandwidth) to

separate the RDS signals. This filter uses switched

capacitor technique and is clocked by a clock frequency of

541.5 kHz derived from the 4.332/8.664 MHz crystal

oscillator. Then the signal is fed to the reconstruction filter

to smooth the sampled and filtered RDS signal before it is

output on pin 8. The signal is AC-coupled to the

comparator (pin 7). The comparator is clocked with a

frequency of 228 kHz (synchronized by the 57 kHz of the

demodulator).

Timing

Fixed and variable dividers are applied to the

4.332/8.664 MHz crystal oscillator to generate the

1.1875 kHz RDS clock RDCL, which is synchronized by

the incoming data. Which ever clock edge is considered

(positive or negative going edge) the data will remain valid

for 399

s after the clock transition. The timing of data

change is 4

Digital part

s before a clock change. Which clock

transition (positive or negative going clock) the data

change occurs in, depends on the lock conditions and is

arbitrary (bit slip).

During poor reception it is possible that faults in phase

occur, then the clock signal stays uninterrupted, and data

is constant for 1.5 clock periods. Normally, faults in phase

do not occur on a cyclic basis. If however, faults in phase

occur in this way, the minimum spacing between two

possible faults in phase depends on the data being

transmitted. The minimum spacing cannot be less than

16 clock periods. The quality bit changes only at the time

of a data change.

The synchronous demodulator (Costas loop circuit) with

carrier regeneration demodulates the internal coupled,

digitized signal. The suppressed carrier is recovered from

the two sidebands (Costas loop). The demodulated signal

is low-pass-filtered in such a way that the overall pulse

shape (transmitter and receiver) approaches a

cosinusoidal form in conjunction with the following

Integrate and dump circuit.

The data-spectrum shaping is split into two equal parts and

handled in the transmitter and in the receiver. Ideally, the

data filtering should be equal in both of these parts.

1997 Feb 24

Notes

1. Equivalent to discharging a 200 pF capacitor via a 0

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