62C256.PDF
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cy62256.fm
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CY62256
32Kx8 Static RAM
Features
output enable (OE) and three-state drivers. This device has an
automatic power-down feature, reducing the power consump-
tion by 99.9% when deselected. The CY62256 is in the stan-
dard 450-mil-wide (300-mil body width) SOIC, TSOP, and
600-mil PDIP packages.
An active LOW write enable signal (WE)
co
ntrol
s th
e writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O
0
through I/O
7
) is written into the memory location addressed by
the address present on the address pins (A
0
through A
14
).
Reading the device is ac
com
plish
ed b
y selecting the de
vice
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
t
he c
hip is selected, outputs are enabled, and write enable
(WE) is HIGH.
W (max.)
• 55, 70 ns access time
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
m
The CY62256 is a high-performance CMOS static RAM orga-
nized as 32,768 words by 8 bits. Easy
mem
ory expansion is
provided by an active LOW chip enable (CE) and active LOW
Logic Block Diagram
Pin Configurations
SOIC/DIP
A
5
1
2
3
4
5
6
7
8
9
10
11
28
27
26
V
CC
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
WE
I/O
0
A
A
3
A
2
A
1
25
INPUTBUFFER
24
23
22
A
10
I/O
1
A
9
A
8
A
A
A
5
A
A
3
A
2
OE
A
0
I/O
2
21
20
19
18
17
CE
I/O
3
512x512
ARRAY
A
14
I/O
7
I/O
6
I/O
5
I/O
4
I/O
0
I/O
1
I/O
2
I/O
4
12
13
16
I/O
5
GND
14
15
I/O
3
C62256–2
CE
I/O
6
WE
COLUMN
DECODER
POWER
DOWN
I/O
7
OE
C62256–1
A
11
7
6
8
9
A
12
OE
A
1
A
2
A
A
4
WE
V
C
A
A
6
A
A
8
A
9
22
23
24
25
26
27
28
1
2
21
A
0
CE
I/O
7
I/O
6
I/O
5
A
10
A
13
20
A
14
A
9
5
10
11
19
18
17
A
8
I/O
0
4
A
7
3
TSOP I
12
I/O
1
I/O
4
A
6
13
I/O
2
TSOP I
Top View
(not to scale)
16
2
Reverse Pinout
I/O
3
A
5
1
14
GND
15
14
13
12
Top View
(not to scale)
GND
I/O
2
I/O
1
V
CC
28
15
I/O
3
WE
27
16
I/O
4
A
4
26
17
I/O
5
3
4
I/O
0
A
14
A
3
25
18
I/O
6
11
A
2
24
19
I/O
7
5
10
9
A
13
A
12
C62256–3
A
1
23
20
21
CE
A
10
A
11
6
OE
22
A
0
7
8
C62256–4
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 1996 – Revised November 26, 1997
• 4.5V–5.5V Operation
• Low active power (70 ns, LL version)
— 275 mW (max.)
• Low standby power (70 ns, LL version)
—
28
Top V
i
ew
CY62256
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... -
65
°
C to +150
°
C
Ambient Temperature with
Power Applied ................................................... 0
°
C to +70
°
C
Operating Range
Range
Ambient Temperature
V
CC
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)
.................................................-
0.5V to +7.0V
Commercial
0
°
C to +70
°
C
5V
±
10%
DC Voltage Applied to Outputs
in High Z State
[1]
Industrial
–40
°
C to +85
°
C
5V
±
10%
....................................... -
0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................... -
0.5V to V
CC
+ 0.5V
Electrical Characteristics
Over the Operating Range
CY62256
-
55
CY62256
-
70
Parameter
Description
Test Conditions
Min. Typ
[2]
Max.
Min. Typ
[2]
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
=
-
1.0 mA 2.4
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 2.1 mA
0.4
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+0.5V
2.2
V
CC
+0.5V
V
V
IL
Input LOW Voltage
-
0.5
0.8
-
0.5
0.8
V
I
IX
Input Load Current
GND
<
V
I
<
V
CC
-
0.5
+0.5
-
0.5
+0.5
m
A
I
OZ
Output Leakage
Current
GND
<
V
O
<
V
CC
, Output Dis-
abled
-
0.5
+0.5
-
0.5
+0.5
m
A
I
CC
V
CC
Operating Supply
Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
28
55
28
55
mA
L
25
50
25
50
mA
LL
25
50
25
50
mA
I
SB1
Automatic CE
Power-Down Current—
TTL Inputs
Max. V
CC
, CE
>
V
IH
,
V
IN
>
V
IH
or
V
IN
<
V
IL
, f = f
MAX
0.5
2
0.5
2
mA
L
0.4
0.6
0.4
0.6
mA
LL
0.3
0.5
0.3
0.5
mA
I
SB2
Automatic CE
Power-Down Current—
CMOS Inputs
Ma
x. V
CC
,
CE
>
V
CC
1
5
1
5
mA
-
0.3V
L
2
50
2
50
m
A
0.3V
or V
IN
<
0.3V, f = 0
-
LL
0.1
5
0.1
5
m
A
Indust’l Temp Range LL
0.1
10
0.1
10
m
A
Shaded area contains preliminary information.
Capacitance
[3]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
C, f = 1 MHz,
V
CC
= 5.0V
°
6
pF
C
OUT
Output Capacitance
8
pF
2.0V for pulse durations of less than 20 ns.
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(T
A
= 25
-
C, V
CC
). Parameters are guaranteed by design and characterization, and not 100% tested.
3. Tested initially and after any design or process changes that may affect these parameters.
°
2
V
IN
>
V
CC
T
A
= 25
Note:
1. V
IL
(min.)
=
CY62256
AC Test Loads and Waveforms
R1 180
0
W
R1 1800
W
5V
OUTPUT
5V
OUTPUT
ALL INPUT PULSES
3.0V
90%
9
0
%
10%
10%
R2
990
R2
990
100 pF
5pF
GND
W
W
<
5ns
<5ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C62256–5
C62256–6
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
639
W
OUTPUT
1.77V
Data Retention Characteristics
Parameter
Description
Conditions
[4]
Min.
Typ.
[2]
Max.
Unit
V
DR
V
CC
for Data Retention
V
CC
= 3.0V,
CE
>
V
CC
2.0
V
-
0.3V,
I
CCDR
Data Retention Current
L
2
50
m
A
V
IN
>
V
CC
-
0.3V or
LL
V
IN
<
0.3V
0.1
5
m
A
LL Indust’l
0.1
10
m
A
t
CDR
[3]
Chip Deselect to Data
Retention Time
0
ns
t
R
[3]
Operation Recovery Time
t
RC
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
V
DR
>
2V
3.0V
t
R
CE
C62256–7
Note:
4. No input may exceed V
CC
+0.5V.
3
CY62256
Switching Characteristics
Over the Operating Range
[5]
CY62256
-
55
CY62256
70
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
55
70
ns
t
AA
Address to Data Valid
55
70
ns
t
OHA
Data Hold from Address Change
5
5
ns
t
ACE
CE LOW to Data Valid
55
70
ns
t
DOE
OE LOW to Data Valid
25
35
ns
t
LZOE
OE LOW to Low Z
[6]
5
5
ns
t
HZOE
OE HIGH to High Z
[6, 7]
20
25
ns
t
LZCE
CE LOW to Low Z
[6]
5
5
ns
t
HZCE
CE HIGH to High Z
[6, 7]
20
25
ns
t
PU
CE LOW to Power-Up
0
0
ns
t
PD
CE HIGH to Power-Down
55
70
ns
WRITE CYCLE
[8, 9]
t
WC
Write Cycle Time
55
70
ns
t
SCE
CE LOW to Write End
45
60
ns
t
AW
Address Set-Up to Write End
45
60
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
ns
t
PWE
WE Pulse Width
40
50
ns
t
SD
Data Set-Up to Write End
25
30
ns
t
HD
Data Hold from Write End
0
0
ns
t
HZWE
WE LOW to High Z
[6, 7]
20
25
ns
t
LZWE
WE HIGH to Low Z
[6]
5
5
ns
Shaded area contains preliminary information.
Switching Waveforms
Read Cycle No. 1
[10,11]
t
RC
ADDRESS
t
OHA
t
AA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C62256–8
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of A
C Te
st Loads.
Trans
ition is measured
±
500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold
timi
ng should b
e re
ferenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for
wr
it
e c
ycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
10.
Dev
ice is continuously selected. OE, CE = V
IL
.
11. WE is HIGH for read cycle.
4
-
CY62256
Switching Waveforms
(continued)
Read Cycle No. 2
[11,12]
t
RC
CE
t
ACE
OE
t
DOE
t
HZOE
t
HZCE
t
LZOE
HIGH
DATA OUT
HIGH IMPEDANCE
DATA VALID
IMPEDAN
CE
t
LZCE
t
PU
t
PD
V
CC
SUPPLY
CURRENT
ICC
50%
50%
ISB
C62256–9
Write Cycle No. 1 (WE Controlled)
[8,13,14]
t
WC
ADDRESS
CE
t
AW
t
HA
WE
t
SA
t
PWE
OE
t
SD
t
HD
DATA I/O
NOTE
15
DATA
IN
VALID
t
HZOE
C62256–10
Write Cycle No.
2
(CE Controlled)
[8,13,14]
t
WC
ADDRES
S
CE
t
SCE
t
SA
t
AW
t
HA
WE
t
SD
t
HD
DATA I/O
DATA
IN
VALID
C62256–11
Notes:
12. Address valid prior to or coinc
ide
nt with CE transition LOW.
13. D
ata
I/O is high impedance if OE =
V
IH
.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
5
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